MSC8144ADS Freescale, MSC8144ADS Datasheet - Page 49

• Manufacturer Part Number: MSC8144ADS
• Manufacturer: Freescale

Specifications of MSC8144ADS

• Lead Free Status / RoHS Status: Compliant

5.14.2 BCSR1 Board Control Register 1
On the board, the BCSR1 acts as a control register. The BCSR1, which may be read or written at
any time, receives its defaults upon Power-On-Reset. The BCSR1 fields are described below in
Table 5-10:
5.14.3 BCSR2 Board Control Register 2
On the board, the BCSR2 acts as a control reset register. The BCSR2, which may be read or
written at any time, receives its defaults upon Power-On-Reset. All reset signals mentioned
Freescale Semiconductor
BIT
0
1
2
3
4
5
6
7
TDMSHREN
BOOTSQEN
MNEMONIC
TDMTSTEN
RGMII1EN
RGMII2EN
SorRGMII
UTPHEN
GE1EN
Table 5-10. BCSR1 Peripheral Control 2 (Offset 1)
TDM Test Clock Buffer Enable. TDM Clock/Sync generated by
internal counter will apply to MSC8144 TDM port when this bit is low.
When this bit is high, it will disable the clock buffer. Other TDM
on-board clock sources (CODEC, E1T1 Framers, DS3) are still
available.
TDM Test Clock in Shared Mode. TDM Clock/Sync generated by
internal counter will apply to MSC8144 TDM port 0 in shared mode
when this bit is low. When this bit is high, it will disable the clock buffer.
CODEC will provide clocks to TDM port 0.
GE1 Bus Switch Select RGMII. When low GE1 port signals are tied
to RGMII peripherals. If high low speed I/F such PCI/UTP are
selected.
GE2 Bus Switch Select RGMII. When low GE2 port signals are tied
to RGMII peripherals. If high low speed I/F such PCI/UTP are
selected.
GE1 Port Bus Switch Disable. When low GE1 port functions in
normal mode. If high the reference clock 125MHz is disabled.
Host Utopia Mode. When low Host Utopia port is selected. If high a
buffer isolates CPM Utopia signals to available I
signals.
GETH Phy Mode Select. This bit provides the configuration sequence
to GETH phy Port 3. Low configures the Phy to SGMII-to-Cooper
Mode, high - sets it in RGMII-to-Copper Mode.
Host Boot Sequencer Enable. Low enables boot from Serial
EEPROM during reset, when high Boot Sequencer is disabled - no
boot configuration initializes code.
MSC8144ADS MSC8144, Rev. 0
Function
Board Control and Status Registers (BCSRs)
2
C2 port over Utopia
SW2.2
DEF
1
1
0
0
0
1
1
ATT.
R,W
R,W
R,W
R,W
R,W
R,W
R,W
R,W
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