MSC8144ADS Freescale, MSC8144ADS Datasheet - Page 41

• Manufacturer Part Number: MSC8144ADS
• Manufacturer: Freescale

Specifications of MSC8144ADS

• Lead Free Status / RoHS Status: Compliant

5.11
The JTAG debug connectivity scheme is shown in Figure 5-12 The MSC8144 has two options
for JTAG: both processors connected in a chain, and both (or one) processors connected
independently. If both processors are connected in a chain (set SW2[3] = 0, or BCSR3[5] = 0),
only the OnCE 14-pin connector is used. The command chain flows via the MSC8144 to the
MPC8560, and both processors are viewed as one entity via CodeWarrior. If the processors are
connected separately (set SW2[3] = 1, or BCSR3[5] = 1), then use the OnCE connector for the
MSC8144, and the COP 16-pin connector for the MPC8560. This second option allows the user
to focus on debugging the MSC8144 only, without the distraction of code from the MPC8560.
5.12
The Host processor, the MPC8560, is a member of the PowerQUICC III family of network
processors. The MPC8560 integrates two processing blocks—a high-performance embedded
e500 core, and a communications processor module (CPM). Below is a list of MPC8560 ports
used on the ADS:
Freescale Semiconductor
„ DDR controller in 64-bit Mode at 266MHz;
„ LBC bus;
„ 64-bit PCI controller configured in 32-bit mode;
„ Two integrated TSEC 1Gbps in RGMII mode.
„ CPM SPI port in multi-master mode;
„ CPM FCC1 Utopia bus;
JTAG Debug Port Connectivity
Host Processor
Debug
Host 2
ADS
EE0
EE1
EE2
MSC8144
Figure 5-12. JTAG Multiplexing
MSC8144ADS MSC8144, Rev. 0
JTAG
JTAG
contr
FPGA
Mux
JTAG
MPC8560
Reset Operation and Configuration
Debug
Host 1
5-17