TSEV81102G0TPZR3 E2V, TSEV81102G0TPZR3 Datasheet - Page 15

no-image

TSEV81102G0TPZR3

Manufacturer Part Number
TSEV81102G0TPZR3
Description
Manufacturer
E2V
Datasheet

Specifications of TSEV81102G0TPZR3

Lead Free Status / RoHS Status
Not Compliant
Table 5-4.
2105D–BDC–07/05
Parameter
Synchronous Reset
Setup time from SyncReset to Clkln
Hold time from Clkln to SyncReset
Rise/fall for (10% – 90%)
Input Data
Setup time from I[0…9] to Clkln
Hold time from Clkln to I[0…9]
Rise/fall for (10% – 90%)
Output Data
Data output delay
Data pipeline delay
Rise/fall for (10% – 90%)
Data Ready
Clock to data ready falling edge
Clock to data ready rising edge
Asynchronous reset to DataReady delay
Synchronous reset to DataReady delay
Rise/fall for (10% – 90%)
Rising edge uncertainty
Setup time from Bist to Clkln
DR input clock
DR/2 input clock
DR input clock
DR/2 input clock
DR input clock
DR/2 input clock
DR input clock
DR/2 input clock
DR input clock
DR/2 input clock
DR input clock, 1:4 ratio
DR input clock, 1:8 ratio
DR/2 input clock, 1:4 ratio
DR/2 input clock, 1:8 ratio
DR input clock
DR/2 input clock
DR input clock
DR/2 input clock
Switching Performances (Continued)
TROD/TFOD
TRDR/TFDR
TSRR/TFSR
TRDI/TFDI
TSCKIN
THCKIN
Symbol
TSRDR
JITTER
TSBIST
TARDR
THSR
TDRR
TSSR
TDRF
TOD
TPD
Level
Test
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
Min
100
100
500/500
380/260
Value
1000
1820
1720
3080
2500
3180
2750
2820
1500
1000
-580
-480
-800
-690
Typ
780
680
890
3/2
7/2
20
3
7
Max
TS81102G0
Number
of input
ps rms
clock
Unit
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
Note
(10)
(11)
(12)
(13)
(14)
(15)
(16)
(17)
(18)
(19)
(20)
(21)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
15