TSEV81102G0TPZR3 E2V, TSEV81102G0TPZR3 Datasheet - Page 7

• Manufacturer Part Number: TSEV81102G0TPZR3
• Manufacturer: E2V

Specifications of TSEV81102G0TPZR3

• Lead Free Status / RoHS Status: Not Compliant

4.6
4.7
4.8
4.9
2105D–BDC–07/05
Counter Programmable State
Pipeline Delay
8-/10-bit, with NAP Mode for the 2 Unused Bit
ECL Differential Input Data
The front edge of this clock is synchronized with Clkln inside the DMUX, and generates a 200 ps
reset pulse. This reset pulse occurs during a fixed level of Clkln.
If the DMUX was synchronized with Syncreset previous to a possible loss of synchronization,
then the output data is immediately correct, no modification can be seen at the output of the
DMUX, and no data is lost
If the DMUX was not synchronized with SyncReset previous to a possible loss of synchroniza-
tion, then the output data and data ready of the DMUX are changed. The output data is correct
after a number of input clocks corresponding to the pipeline delay
chronous Reset” on page
When the counter is reset, its initial states depends on the conversion ratio:
The maximum pipeline delay depends on the conversion ratio:
The DMUX is a 10-bit parallel device. The last two bits (bits 8 and 9) may not be used, and the
corresponding functions are set to nap mode to reduce power consumption.
Input data are ECL compatible (Voh = -0.8V, Vol = -1.8V).
The minimum swing required is 100 mV differential.
All inputs have a 100Ω differential termination resistor. The middle point of these resistors is
connected to ground through a 10 pF capacitor.
Figure 4-5.
• 1:8: counting on 8 bits
• 1:4: counting on 4 bits
• 1:8: pipeline delay = 7
• 1:4: pipeline delay = 3
ECL Differential Input Data
20).
(”Internal Timing Diagram” on page
ClkIn
50Ω
10 pF
Gnd
Gnd
50Ω
ClkInb
3).
(”Timing Diagrams with Syn-
TS81102G0
7