TSEV81102G0TPZR3 E2V, TSEV81102G0TPZR3 Datasheet - Page 17

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TSEV81102G0TPZR3

Manufacturer Part Number
TSEV81102G0TPZR3
Description
Manufacturer
E2V
Datasheet

Specifications of TSEV81102G0TPZR3

Lead Free Status / RoHS Status
Not Compliant
5.5
5.5.1
Figure 5-1.
2105D–BDC–07/05
Explanation of Test Levels
Input Clock Timings
Data [0..9]
Input Clock
Clkln
TRCKIN
TFCKIN
Table 5-5.
Notes:
d1
TC2
TC1
Clkln Type = 1
DataReady Mode (DR)
Num
1
2
3
4
5
TSCKIN
d2
1. The level 1 and 2 tests are performed at 50 MHz.
2. Only MIN and MAX values are guaranteed (typical values are issuing from characterization
results).
Characteristics
100% production tested at +25
100% production tested at +25
Sample tested only at specified temperatures.
Parameter is guaranteed by design and characterization testing (thermal steady-state
conditions at specified temperature).
Parameter is a typical value only.
d3
Explanation of Test Levels
THCKIN
d4
d5
°
°
C.
C, and sample tested at specified temperatures.
(1)
TRCKIN
TFCKIN
d1
TC2
TC1
Clkln Type = 0
DataReady/2 Mode (DR/2)
TSCKIN
d2
d3
THCKIN
TS81102G0
d4
d5
(1)
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