TSEV81102G0TPZR3 E2V, TSEV81102G0TPZR3 Datasheet - Page 3

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TSEV81102G0TPZR3

Manufacturer Part Number
TSEV81102G0TPZR3
Description
Manufacturer
E2V
Datasheet

Specifications of TSEV81102G0TPZR3

Lead Free Status / RoHS Status
Not Compliant
2. Internal Timing Diagram
Figure 2-1.
2105D–BDC–07/05
Synchronous reset = Fs/8
DR/2 In = Fs/2 = ClkPar
Internal reset pulse
Master Even Latch
Master Odd Latch
Slave Even Latch
Slave Odd Latch
A to H LatchOut
A to H Port Out
Latch Select G
Latch Select H
Latch Select A
Latch Select B
Output Port H
Output Port A
Output Port B
Port Select G
Port Select H
Port Select A
Port Select B
Internal Timing Diagram
DR In = Fs
Data In
DROut
This diagram corresponds to an established operation of the DMUX with Synchronous Reset.
N
N
N+1
N+1
N
500 ps min
N+2
N+1
N+2
N+3
N+2
N+3
N+4
N+3
N+4
N
N+5
N+4
N+1
N+5
N+6
N+5
N+6
N+7
N+6
N+7
N+8
N+7
N+8
N+9
N+8
N+9
N+10 N+11 N+12 N+13 N+14 N+15 N+16 N+17 N+18 N+19 N+20 N+21 N+22 N+23 N+24
N+6
N+9
N+10
N to N+7
N+10
N+7
N+1
N+7
N+11
N
N+11
N+8
N+12
N+12
N+9
N+13
N+13
N+14
N+14
N+15
N+15
N+16
N+16
N+17
N+14
N+17
N+18
N+8 to N+15
N+15
N+15
N+8
N+9
N+18
N+19
N+16
N+19
N+20
N+20
N+17
N+21
N+21
N+22
N+22
N+23
N+23
N+24
N+25 N+26 N+27 N+28 N+29 N+30 N+31
N+24
N+25
TS81102G0
N+22
N+25
N+26
N+16 to N+23
N+23
N+16
N+17
N+23
N+26
N+27
N+24
N+27
N+28
N+25
N+28
N+29
N+29
N+30
N+30
N+31
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