TSEV81102G0TPZR3 E2V, TSEV81102G0TPZR3 Datasheet - Page 18

• Manufacturer Part Number: TSEV81102G0TPZR3
• Manufacturer: E2V

Specifications of TSEV81102G0TPZR3

• Lead Free Status / RoHS Status: Not Compliant

5.5.2
Figure 5-2.
5.5.3
Figure 5-3.
18
(not available out of the DEMUX)
TS81102G0
ADC Delay Adjust Timing Diagram
Timing Diagrams with Asynchronous Reset
ADC Delay Adjust Timing Diagram
Start with Asynchronous Rest, 1:8 Ratio, DR Mode
Internal Port Selection
ADCDelAdjOut
ADCDelAdjIn
ASyncReset
TFOADA
TC2ADA
TC1ADA
TRIADA
TFIADA
G[0..9]
C[0..9]
D[0..9]
H[0..9]
A[0..9]
B[0..9]
E[0..9]
F[0..9]
I[0..9]
Clkn
With a nominal tuning of DMUXDelAdj at a frequency of 1.5 GHz, d1 and d2 data is lost because
of the internal clock’s path propagation delay TCPD. TCPD is tuned with DMUXDelAdjCtrl pins
to obtain good setup and hold times between Clkln and the data.
With a nominal tuning of DMUXDelAdj at 1.5 GHz, d1 and d2 data is lost because of the internal
clock’s path propagation delay TCPD. TCPD is tuned with DMUXDelAdjCtrl pins to obtain good
setup and hold times between Clkln and the input data. This timing diagram does not change
with the opposite phase of Clkln.
DR
TARDR
PWAR
A
d1
TCPD
d2
d3
B
TDRR
d4
C
TROADA
d5
D
d6
E
d7
F
TOD
TDRF
d8
G
d9
H
d10
A
d11
B
TPD
d12
C
TRDR
TADA
d13
d3
d4
d5
d6
d7
d8
d9
D
d14
E
TROD/TFOD
d15
F
TOD
d16
G
TFDR
d17
2105D–BDC–07/05
d10
d11
d12
d13
d14
d15
d16
d17
H