TSEV81102G0TPZR3 E2V, TSEV81102G0TPZR3 Datasheet - Page 36

• Manufacturer Part Number: TSEV81102G0TPZR3
• Manufacturer: E2V

Specifications of TSEV81102G0TPZR3

• Lead Free Status / RoHS Status: Not Compliant

10.4
Figure 10-5. Synchronous Reset Operation in DR/2 Mode, 1:4 ratio, 375 MHz (Full-speed) – Principle of Operation
Figure 10-6. Synchronous Reset Operation in DR/2 Mode, 1:4 ratio, 375 MHz (Full-speed) – Timings
Note:
If the reset rising edge had occurred in the first allowed window (on the left), the reset would have been effective on the first
represented clock rising edge (first clock rising edge of the schematic, on the left of the edge represented with the arrow).
Figure 10-7. Synchronous Reset Operation in DR/2 Mode, 1:8 ratio, 750 MHz (Full-speed) – Principle of Operation
36
Allowed for the
Sync_RESET
Times Zones
Operation in DR/2 Mode
The clock edge to which the reset applies is the one identified by the arrow.
TS81102G0
reset
Fs/2
Sync_RESET
Sync_RESET
Fs/2
Fs/2
In DR/2 mode, the DMUX input clock can run at up to 750 MHz in 1:8 ratio or 375 MHz in 1:4
ratio, since the DR/2 clock from the ADC is half the sampling frequency.
Both cases are described in the following timing diagrams.
480 ps
1.333 ns
5.32 ns
680 ps
680 ps min
5.32 ns
1.333 ns
480 ps
680 ps
1333 ps
2105D–BDC–07/05