LAN9303-ABZJ Standard Microsystems (SMSC), LAN9303-ABZJ Datasheet - Page 142

• Manufacturer Part Number: LAN9303-ABZJ
• Manufacturer: Standard Microsystems (SMSC)

Specifications of LAN9303-ABZJ

• Number Of Primary Switch Ports: 3
• Operating Supply Voltage (typ): 3.3V
• Fiber Support: No
• Power Supply Type: Analog
• Data Rate (typ): 10/100Mbps
• Vlan Support: Yes
• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Mounting: Surface Mount
• Jtag Support: No
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Operating Temperature Classification: Commercial
• Data Rate: 100Mbps
• Lead Free Status / RoHS Status: Compliant

Revision 1.4 (07-07-10)
13.2.1.2
25:20
18:13
BITS
11:0
31
30
29
28
27
26
19
12
Software Interrupt (SW_INT)
This interrupt is generated when the
(SW_INT_EN)
Writing a one clears this interrupt.
Device Ready (READY)
This interrupt indicates that the device is ready to be accessed after a
power-up or reset condition.
RESERVED
Switch Fabric Interrupt Event (SWITCH_INT)
This bit indicates an interrupt event from the Switch Fabric. This bit should
be used in conjunction with the
(SW_IPR)
Fabric.
Port 2 PHY Interrupt Event (PHY_INT2)
This bit indicates an interrupt event from the Port 2 PHY. The source of the
interrupt can be determined by polling the
Flags Register
Port 1 PHY Interrupt Event (PHY_INT1)
This bit indicates an interrupt event from the Port 1 PHY. The source of the
interrupt can be determined by polling the
Flags Register
RESERVED
GP Timer (GPT_INT)
This interrupt is issued when the
(GPT_CNT)
RESERVED
GPIO Interrupt Event (GPIO)
This bit indicates an interrupt event from the General Purpose I/O. The
source of the interrupt can be determined by polling the
I/O Interrupt Status and Enable Register (GPIO_INT_STS_EN)
RESERVED
Interrupt Status Register (INT_STS)
This register contains the current status of the generated interrupts. A value of 1 indicates the
corresponding interrupt conditions have been met, while a value of 0 indicates the interrupt conditions
have not been met. The bits of this register reflect the status of the interrupt source regardless of
whether the source has been enabled as an interrupt in the
indicated as R/WC, writing a 1 to the corresponding bits acknowledges and clears the interrupt.
to determine the source of the interrupt event within the Switch
Offset:
wraps past zero to FFFFh.
bit of the
(PHY_INTERRUPT_SOURCE_x).
(PHY_INTERRUPT_SOURCE_x).
Interrupt Enable Register (INT_EN)
058h
DESCRIPTION
Small Form Factor Three Port 10/100 Managed Ethernet Switch with Single MII/RMII/Turbo MII
Switch Global Interrupt Pending Register
General Purpose Timer Count Register
DATASHEET
Software Interrupt Enable
Port x PHY Interrupt Source
Port x PHY Interrupt Source
142
Size:
General Purpose
is set high.
Interrupt Enable Register
32 bits
R/WC
R/WC
R/WC
TYPE
SMSC LAN9303/LAN9303i
RO
RO
RO
RO
RO
RO
RO
RO
(INT_EN). Where
DEFAULT
Datasheet
0b
0b
0b
0b
0b
0b
0b
-
-
-
-