LAN9303-ABZJ Standard Microsystems (SMSC), LAN9303-ABZJ Datasheet - Page 37

• Manufacturer Part Number: LAN9303-ABZJ
• Manufacturer: Standard Microsystems (SMSC)

Specifications of LAN9303-ABZJ

• Number Of Primary Switch Ports: 3
• Operating Supply Voltage (typ): 3.3V
• Fiber Support: No
• Power Supply Type: Analog
• Data Rate (typ): 10/100Mbps
• Vlan Support: Yes
• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Mounting: Surface Mount
• Jtag Support: No
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Operating Temperature Classification: Commercial
• Data Rate: 100Mbps
• Lead Free Status / RoHS Status: Compliant

Small Form Factor Three Port 10/100 Managed Ethernet Switch with Single MII/RMII/Turbo MII
Datasheet
SMSC LAN9303/LAN9303i
PINS
NUM
1
LED 0 Polarity
MDIX Enable
Configuration
Port 1 Auto-
GPIO 0
Note 3.6
NAME
LED 0
Strap
and
Configuration strap pins are identified by an underlined symbol name. Configuration strap
values are latched on power-on reset or nRST de-assertion. In addition to the configuration
strap pins that control GPIO/LED and Auto-MDIX operation listed in
configuration strap pins are associated with Port 0 and control its operation. They are
described in
EEPROM Loader. Please refer to
further information.
Table 3.5 GPIO/LED/Configuration Straps (continued)
AMDIX1_LED0P
SYMBOL
GPIO0
LED0
Table
3.4. Some configuration straps can be overridden by values from the
DATASHEET
BUFFER
IS/O12/
OD12/
TYPE
OD12
OS12
O12/
(PU)
(PU)
IS
37
Section 4.2.4, "Configuration Straps," on page 45
This pin is configured to operate as an LED when
the LED 0 Enable bit in the
Register (LED_CFG)
depends on the setting of the field in the
Configuration Register (LED_CFG)
configured to be either an push-pull or open-
drain/open-source output. When selected as an
open-drain/open-source output, the polarity of this
pin depends up the
sampled at reset.
This pin is configured to operate as a GPIO when
the LED 0 Enable bit of the
Register (LED_CFG)
programmable as either a push-pull output, an
open-drain output, or a Schmitt-triggered input by
writing the
Register (GPIO_CFG)
I/O Data & Direction Register
This strap configures the default for the Auto-MDIX
soft-strap for LAN Port 1, as well as the polarity of
the LED 0 pin when it is an open-drain or open-
source output. See
The strap value determines whether or not LAN
Port 1 Auto-MDIX is enabled as follows:
0 = Disabled
1 = Enabled
For LED 0, If the strap value is 0:
The LED is set as active high, since it is assumed
that a LED to ground is used as the pull-down.
If the strap value is 1:
The LED is set as active low, since it is assumed
that a LED to VDD is used as the pull-up.
General Purpose I/O Configuration
DESCRIPTION
Note
AMDIX1_LED0P
is set. The buffer type
is clear. The pin is fully
and the
3.6.
LED Configuration
LED Configuration
(GPIO_DATA_DIR).
General Purpose
Revision 1.4 (07-07-10)
and is
strap value
Table
LED
3.5,
for