LAN9303-ABZJ Standard Microsystems (SMSC), LAN9303-ABZJ Datasheet - Page 88

• Manufacturer Part Number: LAN9303-ABZJ
• Manufacturer: Standard Microsystems (SMSC)

Specifications of LAN9303-ABZJ

• Number Of Primary Switch Ports: 3
• Operating Supply Voltage (typ): 3.3V
• Fiber Support: No
• Power Supply Type: Analog
• Data Rate (typ): 10/100Mbps
• Vlan Support: Yes
• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Mounting: Surface Mount
• Jtag Support: No
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Operating Temperature Classification: Commercial
• Data Rate: 100Mbps
• Lead Free Status / RoHS Status: Compliant

Chapter 7 Ethernet PHYs
Revision 1.4 (07-07-10)
7.1
7.1.1
phy_addr_sel_strap
The device contains three PHYs: Port 1 PHY, Port 2 PHY and a Virtual PHY. The Port 1 & 2 PHYs
are identical in functionality and each connect their corresponding Ethernet signal pins to the Switch
Fabric MAC of their respective port. These PHYs interface with their respective MAC via an internal
MII interface. The Virtual PHY provides the virtual functionality of a PHY and allows connection of an
external MAC to Port 0 of the Switch Fabric as if it was connected to a single port PHY. All PHYs
comply with the IEEE 802.3 Physical Layer for Twisted Pair Ethernet and can be configured for full/half
duplex 100 Mbps (100BASE-TX) or 10Mbps (10BASE-T) Ethernet operation. All PHY registers follow
the IEEE 802.3 (clause 22.2.4) specified MII management register set and can be configured indirectly
via the external MII interface signals, or directly via the memory mapped Virtual PHY registers. In
addition, the Port 1 PHY and Port 2 PHY can be configured via the PHY Management Interface (PMI).
Refer to
registers.
The Ethernet PHYs are discussed in detail in the following sections:
PHY Addressing
Each individual PHY is assigned a unique default PHY address via the
configuration strap as shown in
be changed via the
(PHY_SPECIAL_MODES_x). For proper operation, all PHY addresses must be unique. No check is
performed to assure each PHY is set to a different address. Configuration strap values are latched
upon the de-assertion of a chip-level reset as described in
page
Functional Overview
0
1
Section 7.2, "Port 1 & 2 PHYs," on page 89
Section 7.3, "Virtual PHY," on page 102
45.
Section 13.3, "Ethernet PHY Control and Status Registers"
VIRTUAL PHY DEFAULT
Table 7.1 Default PHY Serial MII Addressing
ADDRESS VALUE
PHY Address (PHYADD)
Small Form Factor Three Port 10/100 Managed Ethernet Switch with Single MII/RMII/Turbo MII
0
1
Table
DATASHEET
7.1. In addition, the Port 1 PHY and Port 2 PHY addresses can
88
PORT 1 PHY DEFAULT
field in the
ADDRESS VALUE
1
2
Section 4.2.4, "Configuration Straps," on
Port x PHY Special Modes Register
for details on the Ethernet PHY
PORT 2 PHY DEFAULT
SMSC LAN9303/LAN9303i
ADDRESS VALUE
phy_addr_sel_strap
2
3
Datasheet