TTSV04622V2-DB LSI, TTSV04622V2-DB Datasheet - Page 4

• Manufacturer Part Number: TTSV04622V2-DB
• Manufacturer: LSI

Specifications of TTSV04622V2-DB

• Number Of Transceivers: 1
• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Not Compliant

TDCS4810G SONET/SDH
Advance Data Sheet
May 2001
10 Gbits/s APS Port and TSI
List of Tables
Contents
Page
Table 1. Pin Assignments for 792-Pin LBGA by Pin Number Order......................................................................... 9
Table 2. Pin Assignments for 792-Pin LBGA by Signal Name Order ..................................................................... 14
Table 3. Pin Descriptions—Receive Interface ........................................................................................................ 19
Table 4. Pin Descriptions—Transmit Interface ....................................................................................................... 22
Table 5. Pin Descriptions—LVDS Reference Cell Pins.......................................................................................... 25
Table 6. Pin Descriptions—Microprocessor Interface ............................................................................................ 26
Table 7. Pin Descriptions—System Control ........................................................................................................... 27
Table 8. Pin Descriptions—PLL References .......................................................................................................... 28
Table 9. Pin Descriptions—JTAG Interface............................................................................................................ 28
Table 10. Pin Descriptions—Power and Ground.................................................................................................... 29
Table 11. Pin Descriptions—No Connect ............................................................................................................... 31
Table 12. Pin Descriptions—Unused Pins.............................................................................................................. 33
Table 13. Pin Summary .......................................................................................................................................... 34
Table 14. STS-12 Byte Ordering ............................................................................................................................ 35
Table 15. STS-192 Byte Ordering .......................................................................................................................... 35
Table 16. Path Alarm (E1/F1) Information Encoding.............................................................................................. 49
Table 17. Line Alarm (E2) Information Encoding.................................................................................................... 49
Table 18. Memory Map Summary .......................................................................................................................... 54
Table 19. Device Interrupt Status Register (RO).................................................................................................... 57
Table 20. Device Interrupt Status Mask Register (R/W)......................................................................................... 58
Table 21. Channel Alarm Interrupt Status Register (RO) ....................................................................................... 58
Table 22. Channel Alarm Interrupt Status Mask Register (R/W)............................................................................ 59
Table 23. Device-Level Alarm Register (W1C)....................................................................................................... 59
Table 24. Device-Level Alarm Mask Register (R/W) .............................................................................................. 59
Table 25. Device ID Register (RO)......................................................................................................................... 59
Table 26. Device Vintage Register (RO) ................................................................................................................ 60
Table 27. Scratch Pad Register (R/W) ................................................................................................................... 60
Table 28. Device Provisioning Register (R/W) ....................................................................................................... 60
Table 29. Device Control Register (R/W) ............................................................................................................... 61
Table 30. Frame Offset Register (R/W).................................................................................................................. 61
Table 31. Framing Error A1A2 Corrupt Value (R/W) .............................................................................................. 61
Table 32. Number of Columns (R/W) ..................................................................................................................... 61
Table 33. Write Lock Register (R/W)...................................................................................................................... 61
Table 34. Channel Alarm Interrupt Status (Consolidation) Register....................................................................... 62
Table 35. Channel Alarm Interrupt Status Mask Register ...................................................................................... 62
Table 36. Path Status Alarm Interrupt Status (Consolidation) Register ................................................................. 62
Table 37. Path Status Alarm Interrupt Status Mask Register ................................................................................. 62
Table 38. Line Status (E2) Change Alarm (W1C) .................................................................................................. 62
Table 39. Line Status (E2) Change Mask (R/W) .................................................................................................... 63
Table 40. APS (K1K2) Change Alarm (W1C)......................................................................................................... 63
Table 41. APS (K1K2) Change Alarm Mask (R/W) ................................................................................................ 63
Table 42. Connection Memory Switch Alarm (W1C) .............................................................................................. 63
Table 43. Connection Memory Switch Alarm Mask (R/W) ..................................................................................... 63
Table 44. FIFO Thresholds (R/W) .......................................................................................................................... 64
Table 45. Configuration A/B Select (R/W) .............................................................................................................. 64
Table 46. Configuration A/B Readback (RO) ......................................................................................................... 64
Table 47. Configuration C/D Line or Path Switching Mode (R/W).......................................................................... 64
Table 48. Configuration C/D Select (R/W).............................................................................................................. 64
Table 49. Configuration C/D Readback (RO) ......................................................................................................... 64
Table 50. Audit Memory Control (R/W) .................................................................................................................. 65
Table 51. Audit Memory Status (RO) ..................................................................................................................... 65
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