TTSV04622V2-DB LSI, TTSV04622V2-DB Datasheet - Page 77

• Manufacturer Part Number: TTSV04622V2-DB
• Manufacturer: LSI

Specifications of TTSV04622V2-DB

• Number Of Transceivers: 1
• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Not Compliant

May 2001
Agere Systems Inc.
Timing Characteristics
Microprocessor Interface Timing
The I/O timing specifications for the microprocessor interface are given in Table 84. The read and write timing dia-
grams for all three microprocessor interface modes are shown in Figures 20—24.
Table 84. Microprocessor Interface Timing
* This value represents the timing for a transfer error (TA_N = 1, TEA_N = 0). The typical value during normal access would be 9(tc_M360) ns.
tcycle_M860
tcycle_DSP
tc_M860
tc_M360
Symbol
tc_DSP
t10
t11
t12
t13
t14
t15
t16
t17
t18
t19
t20
t21
t22
t23
t24
t25
t26
t27
t28
t29
t30
t31
t1
t2
t3
t4
t5
t6
t7
t8
t9
(Read)
(Read)
Asynch
(Write)
(Write)
(Write)
Synch
Synch
Mode
M860
M360
DSP
Bus Transfer Cycle Time
TA_N/TEA_N Valid to DATA Valid
Bus Transfer Cycle Time
PCLK Period
CS_N, TS_N, RW_N Valid to PCLK
ADDRESS, DATA Valid to PCLK
CS_N, TS_N, RW_N, ADDRESS, DATA Hold
PCLK to TA_N/TEA_N 3-State to High
PCLK to TA_N/TEA_N High to Low
PCLK to TA_N/TEA_N Low to High
PCLK to TA_N/TEA_N 3-State
DATA Valid to PCLK with TA_N Low
PCLK to DATA 3-State
PCLK Period
ADDRESS Valid to CS_N, DS_N, TS_N Fall
TA_N Fall to CS_N, DS_N, TS_N Rise
TA_N Fall to DATA, ADDRESS Invalid
RW_N Fall to CS_N, DS_N, TS_N Fall
DS_N Rise to RW_N Rise
DATA Valid to DS_N Fall
CS_N, DS_N, TS_N Fall to TA_N/TEA_N High
CS_N, DS_N, TS_N Fall to TA_N/TEA_N Fall
CS_N, DS_N, TS_N Rise to TA_N/TEA_N Rise
CS_N, DS_N, TS_N Rise to TA_N/TEA_N 3-
State
CS_N,TS_N, DS_N Rise to DATA 3-State
PCLK Period
CS_N, ADDRESS Valid to PCLK (Setup)
TS_N, RW_N Valid to PCLK (Setup)
CS_N to TA_N Active/High Impedance
PCLK to TA_N (Clock to Out)
PCLK to CS_N, ADDRESS Invalid (Hold)
PCLK to TS_N, RW_N Invalid (Hold)
PCLK to DATA Input Invalid (Hold)
DATA Input Valid to PCLK (Setup)
PCLK to DATA Output Active/High Impedance
PCLK to DATA Output Valid
Parameter
8 (tc_M860) 12 (tc_M860)
2 (tc_M860)
4 (tc_M360)
5 (tc_M360) 35 (tc_M360)*
2 (tc_M360)
4 (tc_M360)
2 (tc_M360)
5 (tc_DSP)
tc_M360
12.76
20.0
Min
10 Gbits/s APS Port and TSI
3.5
3.0
15
18
—
—
—
10
—
—
—
—
4
0
2
2
0
0
0
0
0
0
0
0
0
3 (tc_M860)
3 (tc_M360)
5 (tc_M360)
2 (tc_M360)
4 (tc_M360)
Max
14.0
26.0
9.5
6.0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
4
5
4
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
77