TTSV04622V2-DB LSI, TTSV04622V2-DB Datasheet - Page 46

• Manufacturer Part Number: TTSV04622V2-DB
• Manufacturer: LSI

Specifications of TTSV04622V2-DB

• Number Of Transceivers: 1
• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Not Compliant

10 Gbits/s APS Port and TSI
Functional Description
Receiver Block
AIS Insertion
Receiver behavior under the LOF event is under software control; it is possible to select either insert AIS or pass-
through when an LOF condition occurs (per-channel control). It is also possible to force AIS (per-channel control).
Note that AIS will overwrite all bytes to ones. AIS insertion could be performed at different stages in the receiver. It
was placed before the FIFO aligner since the output of the FIFO aligner will be all ones under any circumstances,
since the CDR macro will always provide a clock when powered up. When the CDR channel is powered down, the
output of the FIFO automatically forces all data to ones.
Cross Connect Block
TSI Memory Organization
The memory is logically organized into two banks. Writes occur to successive locations, rotating through all loca-
tions in one bank (having written 12 bytes from each of the 48 write data inputs) before starting on the other bank.
Reads from each of the 48 read ports are random access and are always performed on the bank that is not being
written to. Since there are 576 STS-1 inputs, each bank contains 576 bytes. The banks are switched at the rate of
6.48 MHz.
Connection Memory
The connection memory is logically organized into four memories: configuration A map C (AC), configuration A
map D (AD), configuration B map C (BC), and configuration B map D (BD). Each memory has one entry for each
STS-1 output. Functionally, the memory is divided into many small memories. Each STS-12 channel uses two sep-
arate memories containing entries for all STS-1s in the channel. One of the memories contains configuration A
(both map C and map D), and the other contains configuration B (both map C and map D). Thus, each memory
holds 24 entries (12 for map C, 12 for map D). This organization is shown in Figure 9
46
PER CHANNEL
SELECTED
PER STS-1
(continued)
(STS-12)
OR
Figure 9. Connection Memory Physical Organization
(continued)
CONFIGURATION A
CONFIGURATION A
CONNECTION MEMORY FOR ONE STS-12 CHANNEL
MAP C
MAP D
10 bits
SELECTED PER CHANNEL (STS-12)
0x0B
0x00
0x17
CONFIGURATION B
CONFIGURATION B
MAP C
MAP D
10 bits
24 bytes
Agere Systems Inc.
May 2001
5-9877r.1(F)