LAN9217-MT Standard Microsystems (SMSC), LAN9217-MT Datasheet - Page 123

• Manufacturer Part Number: LAN9217-MT
• Manufacturer: Standard Microsystems (SMSC)

Specifications of LAN9217-MT

• Operating Supply Voltage (typ): 3.3V
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 100
• Lead Free Status / RoHS Status: Compliant

16-bit High-Performance Single-Chip 10/100 Ethernet Controller with HP Auto-MDIX Support
Datasheet
SMSC LAN9217
6.3
SYMBOL
nCS, nRD
t
t
t
t
t
t
t
t
csdv
acyc
t
csh
asu
adv
don
doff
doh
A[7:5]
A[4:1]
Data Bus
ah
In this mode, performance is improved by allowing up to 16 WORD read cycles back-to-back. PIO
Burst Reads can be performed using Chip Select (nCS) or Read Enable (nRD). Either or both of these
control signals must go high between bursts for the period specified.
Note: The “Data Bus” width is 16 bits
Note: A PIO Burst Read cycle begins when both nCS and nRD are asserted. The cycle ends when
PIO Burst Reads
DESCRIPTION
nCS, nRD Deassertion Time
nCS, nRD Valid to Data Valid
Address Cycle Time
Address Setup to nCS, nRD valid
Address Stable to Data Valid
Address Hold Time
Data Buffer Turn On Time
Data Buffer Turn Off Time
Data Output Hold Time
either or both nCS and nRD are deasserted. They may be asserted and deasserted in any
order.
Figure 6.2 PIO Burst Read Cycle Timing
Table 6.4 PIO Burst Read Timing
DATASHEET
123
MIN
13
45
0
0
0
0
TYP
MAX
Revision 2.7 (03-15-10)
30
40
7
UNITS
ns
ns
ns
ns
ns
ns
ns