LAN9217-MT Standard Microsystems (SMSC), LAN9217-MT Datasheet - Page 33
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LAN9217-MT
Manufacturer Part Number
LAN9217-MT
Description
Manufacturer
Standard Microsystems (SMSC)
Datasheet
1.LAN9217-MT.pdf
(139 pages)
Specifications of LAN9217-MT
Operating Supply Voltage (typ)
3.3V
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
100
Lead Free Status / RoHS Status
Compliant
Available stocks
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16-bit High-Performance Single-Chip 10/100 Ethernet Controller with HP Auto-MDIX Support
Datasheet
SMSC LAN9217
3.8.2.1
The host can disable the EEPROM interface through the GPIO_CFG register. When the interface is
disabled, the EEDIO and ECLK signals can be used as general-purpose outputs, or they may be used
to monitor internal MII signals.
Supported EEPROM Operations
The EEPROM controller supports the following EEPROM operations under host control via the
E2P_CMD register. The operations are commonly supported by “93C46” EEPROM devices. A
description and functional timing diagram is provided below for each operation. Please refer to the
E2P_CMD register description in
page 95
for E2P_CMD field settings for each command.
Busy Bit = 0
EEPROM Write
Figure 3.2 EEPROM Access Flow Diagram
Write Data
Command
Command
Register
Register
Register
Write
Read
Idle
Section 5.3.23, "E2P_CMD – EEPROM Command Register," on
DATASHEET
33
EEPROM Read
Read Data
Command
Command
Register
Register
Register
Write
Read
Idle
Busy Bit = 0
Revision 2.7 (03-15-10)
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