LAN9217-MT Standard Microsystems (SMSC), LAN9217-MT Datasheet - Page 13

• Manufacturer Part Number: LAN9217-MT
• Manufacturer: Standard Microsystems (SMSC)

Specifications of LAN9217-MT

• Operating Supply Voltage (typ): 3.3V
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 100
• Lead Free Status / RoHS Status: Compliant

16-bit High-Performance Single-Chip 10/100 Ethernet Controller with HP Auto-MDIX Support
Datasheet
SMSC LAN9217
1.12
1.13
The host bus interface provides a FIFO interface for the transmit and receive data paths, as well as
an interface for the LAN9217 Control and Status Registers (CSR’s).
The host bus interface is the primary bus for connection to the embedded host system. This interface
models an asynchronous SRAM. TX FIFO, RX FIFO, and CSR’s are accessed through this interface.
Programmed I/O transactions are supported.
The LAN9217 host bus interface supports 16-bit bus transfers. Internally, all data paths are 32-bits
wide. The LAN9217 can be interfaced to either Big-Endian or Little-Endian processors.
The LAN9217 also supports the ability to interface to an external PHY device. This interface is
compatible with all IEEE 802.3 MII compliant physical layer devices. For additional information on the
MII interface and associated signals, please refer to
Switching," on page 43
Host Bus Interface (SRAM Interface)
External MII Interface
for more information.
DATASHEET
13
Section 3.11, "MII Interface - External MII
Revision 2.7 (03-15-10)