PEF81902FV1.1 Lantiq, PEF81902FV1.1 Datasheet - Page 163

• Manufacturer Part Number: PEF81902FV1.1
• Manufacturer: Lantiq

Specifications of PEF81902FV1.1

• Lead Free Status / RoHS Status: Supplier Unconfirmed

XACI
4.4.6
CMDR
Value after reset: 00
RMC
RRES
STI
XTF
Data Sheet
RMC
7
1 =
Transmitter Active Indication
0 =
1 =
CMDR - Command Register
Receive Message Complete
0 =
1 =
Receiver Reset
0 =
1 =
Start Timer
0 =
1 =
Transmit Transparent Frame
0 =
RRES
6
The HDLC receiver is active when RACI = ‘1’. This bit may be
polled. The RACI bit is set active after a begin flag has been
received and is reset after receiving an abort sequence.
The HDLC-transmitter is not active
The HDLC-transmitter is active when XACI = ‘1’. This bit may be
polled. The XACI-bit is active when a XTF-command is issued and
the frame has not been completely transmitted.
inactive
Reaction to RPF (Receive Pool Full) or RME (Receive Message
End) interrupt. By setting this bit, the microcontroller confirms that
it has fetched the data, and indicates that the corresponding space
in the RFIFO may be released.
inactive
HDLC receiver is reset, the RFIFO is cleared of any data.
inactive
The T-SMINT
inactive
H
5
0
â
IX hardware timer is started (see TIMR register).
STI
4
write
149
XTF
3
2
0
Register Description
XME
Address:
1
PEF 81902
2001-11-12
XRES
0
21
H