PEF81902FV1.1 Lantiq, PEF81902FV1.1 Datasheet - Page 165

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PEF81902FV1.1

Manufacturer Part Number
PEF81902FV1.1
Description
Manufacturer
Lantiq
Datasheet

Specifications of PEF81902FV1.1

Lead Free Status / RoHS Status
Supplier Unconfirmed
MDS2-0
RAC
Data Sheet
Note: SAP1, SAP2: two programmable address values for the first received address
byte (in the case of an address field longer than 1 byte);
SAPG = fixed value FC / FE
TEI1, TEI2: two programmable address values for the second (or the only, in the
case of a one-byte address) received address byte; TEIG = fixed value FF
Two different methods of the high byte and/or low byte address comparison can
be selected by setting SAP1.MHA and/or SAP2.MLA (see also description of
these bits in
Mode Select
Determines the message transfer mode of the HDLC controller, as follows
:
MDS2-0 Mode
0
0
0
0
1
1
1
1
Receiver Active
0 =
1 =
0
0
1
1
0
1
1
0
0
1
0
1
0
0
1
1
Chapter 4.4.10
The HDLC data is not evaluated in the receiver
The HDLC receiver is activated
Reserved
Reserved
Non-Auto
mode/8
Non-Auto
mode/16
Extended
transparent
mode
Transparent
mode 0
Transparent
mode 1
Transparent
mode 2
Address
Comparison
1.Byte
TEI1,TEI2
SAP1,SAP2,
SAPG
SAP1,SAP2,
SAPG
H
or
.
Chapter 4.4.11
151
2.Byte
TEI1,TEI2,
TEIG
TEI1,TEI2,
TEIG
respectively).
Remark
One-byte address
compare.
Two-byte address
compare.
No address
compare. All
frames accepted.
High-byte address
compare.
Low-byte address
compare.
Register Description
PEF 81902
2001-11-12
H
.

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