PEF81902FV1.1 Lantiq, PEF81902FV1.1 Datasheet - Page 90

• Manufacturer Part Number: PEF81902FV1.1
• Manufacturer: Lantiq

Specifications of PEF81902FV1.1

• Lead Free Status / RoHS Status: Supplier Unconfirmed

PEF 81902
Functional Description
Start Awaking Uk0
On the receipt of AR in the C/I-channel the U-transceiver sends the awake signal U1W
to start an activation.
Synchronizing
After the successful awake procedure the U-transceiver trains its receiver coefficients
until it is able to detect the signals U2.
Reset
In state ’Reset’ a software-reset is performed.
Test
State “Test” is entered when the unconditional commands C/I=SSP is applied. The test
signal SSP is issued as long as pin SSP is active or C/I=SSP is applied.
Transparent
The transmission line is fully activated. User data is transparently exchanged by U4/U5.
Transparent state is entered in the case of a loopback 2. The downstream device is
informed by C/I code AI that the transparent state has been reached
Note that in contrast to the former IEC-T state machine there is no resynchronization
mechanism. Once loss of framing (LOF) has been detected a deactivation is initiated.
Wait for Info U4H
The NT is synchronized and waits now for the permission (U4H) to go to the
’Transparent’ state.
2.4.8
U-Transceiver Interrupt Structure
The U-Interrupt Status register (ISTAU) contains the interrupt sources of the U-
Transceiver
(Figure
35). Each source can be masked by setting the corresponding bit
of the U-Interrupt Mask register (MASKU) to ’1’. Such masked interrupt status bits are
not indicated when ISTAU is read and do not generate an interrupt request.
The ISTAU register is cleared on read access. The interrupt sources of the ISTAU
register (UCIR, RDS, 1ms) need not be evaluated.
When at time t1 an interrupt source generates an interrupt, all further interrupts are
collected. Reading the ISTAU register clears all interrupts set before t1, even if masked.
All interrupts, which are flagged after t1 remain active. After the ISTAU read access, the
next unmasked interrupt will generate the next interrupt at time t2. After t2 it is possible
to reprogram the MASKU register, so that all interrupts, which arrived between t1 and t2
are accessible.
Data Sheet
76
2001-11-12