LULXT9785MBC.D0S L7WN Intel, LULXT9785MBC.D0S L7WN Datasheet - Page 126

• Manufacturer Part Number: LULXT9785MBC.D0S L7WN
• Manufacturer: Intel

Specifications of LULXT9785MBC.D0S L7WN

• Lead Free Status / RoHS Status: Compliant

126
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
4.5.3
Figure 13. Initialization Sequence
Note:
Power-Down Mode
The LXT9785/LXT9785E incorporates numerous features to maintain the lowest power possible.
The device can be put into a low-power state via Register 0 as well as a near-zero power state with
the power down pin. When in power-down mode, the device is not capable of receiving or
transmitting packets.
The lowest power operation is achieved using the Global power-down pin, which is active High.
This pin powers down every circuit in the device, including all clocks. All registers are unaltered
and maintained when the Global PWRDWN pin is released.
The BGA15 package does not support the PWRDWN pin feature.
Individual ports (software power down) can be powered down using Register bit 0.11. This bit
powers down a significant portion of the port, but clocks to the register section remain active. This
allows the management interface to remain active during register power-down. The power-down
bit is active High.
Reset MDIO Registers to
Control Interface at last
Pass Control to MDIO
MDIO Control
values read at H/W
Hardware Reset
Mode
Interface
Software
Reset?
Yes
Low
Initialize MDIO Registers
Power-up or Reset
Read H/W Control
MDDIS Voltage
Interface
Level?
Disable MDIO Writes
High
Hardware Control
Hardware
Reset?
Mode
Yes
Revision Date: 30-May-2006
Document Number: 249241
Revision Number: 010
Datasheet