LULXT9785MBC.D0S L7WN Intel, LULXT9785MBC.D0S L7WN Datasheet - Page 184

• Manufacturer Part Number: LULXT9785MBC.D0S L7WN
• Manufacturer: Intel

Specifications of LULXT9785MBC.D0S L7WN

• Lead Free Status / RoHS Status: Compliant

184
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Figure 45. SS-SMII - 100BASE-TX Receive Timing
Table 66. SS-SMII - 100BASE-TX Receive Timing Parameters
REFCLK rising edge to RxCLK
rising edge
RxData/RxSYNC output delay
from RxCLK rising edge
RxData/RxSYNC Rise/Fall time
Receive start of /J/ to CRS
asserted
Receive start of /T/ to CRS
de-asserted
NOTE: The table latency values are derived with the hardware configuration pins FIFOSEL[1:0] set at a
1. Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production
2. “BT” signifies bit times at the line rate (that is, BT = 100 ns if using 10BASE-T, BT = 10 ns if using
testing.
100BASE-TX or 100BASE-FX).
default configuration of 00 (32 bits of initial fill).
Parameter
RxSYNC
REFCLK
RxData
RxCLK
TPFI
t
Sym
4
t1
t2
t3
t4
t5
t
1
t
2
Min
1.5
t
3
–
–
–
–
t
3
Typ
1.5
1.0
21
25
–
1
t
Max
3
27
30
–
5
–
Units
BT
BT
ns
ns
ns
t
2
2
5
Revision Date: 30-May-2006
Document Number: 249241
Minimum C
Maximum C
Test Conditions
Revision Number: 010
Datasheet
–
–
–
–
L
L
= 5pF
= 40pF