LULXT9785MBC.D0S L7WN Intel, LULXT9785MBC.D0S L7WN Datasheet - Page 165

• Manufacturer Part Number: LULXT9785MBC.D0S L7WN
• Manufacturer: Intel

Specifications of LULXT9785MBC.D0S L7WN

• Lead Free Status / RoHS Status: Compliant

5.2.2
5.2.2.1
5.2.3
5.2.4
Datasheet
Document Number: 249241
Revision Number: 010
Revision Date: 30-May-2006
Intel recommends filtering the power supply to the analog VCC pins of the LXT9785/LXT9785E.
This has two benefits. First, it keeps digital switching noise out of the analog circuitry inside the
LXT9785/LXT9785E, helping with line performance. Second, if the VCC planes are laid out
correctly, digital switching noise is kept away from external connectors, reducing EMI problems.
The recommended implementation is to break the VCC plane into two sections. The digital section
supplies power to the VCCD and VCCIO pins of the LXT9785/LXT9785E. The analog section
supplies power to the VCCA pins. The break between the two planes should run underneath the
device. In designs with more than one the LXT9785/LXT9785E, a single continuous analog VCC
plane can be used to supply them all.
The digital and analog VCC planes should be joined at one or more points by ferrite beads. The
beads should produce at least a 100 Ω impedance at 100 MHz. Beads should be placed so that
current flow is evenly distributed. The maximum current rating of the beads should be at least
150% of the current that is actually expected to flow through them. A bulk cap (2.2 -10μF) should
be placed on each side of each bead.
In addition, a high-frequency bypass cap (0.01 μF) should be placed near each analog VCC pin.
Power and Ground Plane Layout Considerations
Great care needs to be taken when laying out the power and ground planes.
Chassis Ground
For ESD reasons, it is a good design practice to create a separate chassis ground that encircles the
board and is isolated via moats and keep-out areas from all circuit-ground planes and active
signals. Chassis ground should extend from the RJ-45 connectors to the magnetics, and can be used
to terminate unused signal pairs (Bob Smith termination). In single-point grounding applications,
provide a single connection between chassis and circuit grounds with a 2 kV isolation capacitor. In
multi-point grounding schemes (chassis and circuit grounds joined at multiple points), provide
2 kV isolation to the Bob Smith termination.
MII Terminations
Series termination resistors are required on all the SS-SMII output signals driven by the LXT9785/
LXT9785E. Special trace layout consideration should be used when using the SMII interface. Keep
all traces orthogonal and as short as possible. Whenever possible, route the clock and sync traces
evenly between the longest and shortest data routes. This minimizes round-trip, clock-to-data
delays and allows a larger margin to the setup and hold requirements.
Twisted-Pair Interface
Use the following standard guidelines for a twisted-pair interface:
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Follow the guidelines in the LXT9785 Design and Layout Guide (formerly Application Note
151) for locating the split between the digital and analog VCC planes.
Keep the digital VCC plane away from the TPFOP/N and TPFIP/N signals, the magnetics, and
the RJ-45 connectors.
Place the layers so that the TPFOP/N and TFPIP/N signals can be routed near or next to the
ground plane. For EMI reasons, it is more important to shield TPFOP/N than TPFIP/N.
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
165