LULXT9785MBC.D0S L7WN Intel, LULXT9785MBC.D0S L7WN Datasheet - Page 144

• Manufacturer Part Number: LULXT9785MBC.D0S L7WN
• Manufacturer: Intel

Specifications of LULXT9785MBC.D0S L7WN

• Lead Free Status / RoHS Status: Compliant

144
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
4.9
4.9.1
4.9.2
4.9.2.1
Figure 27. 100BASE-X Frame Format
100 Mbps Operation
100BASE-X Network Operations
During 100BASE-X operation, the LXT9785/LXT9785E transmits and receives 5-bit symbols
across the network link.
is not actively transmitting data, the LXT9785/LXT9785E sends out Idle symbols on the line.
In 100BASE-TX mode, the device scrambles the data and transmits it to the network using MLT-3
line code. The MLT-3 signals received from the network are de-scrambled and decoded, and sent
across the RMII to the MAC.
In 100BASE-FX mode, the LXT9785/LXT9785E transmits and receives NRZI signals across the
LVPECL interface. An external 100BASE-FX transceiver module is required to complete the fiber
connection.
As shown in
LXT9785/LXT9785E detects the start of preamble, it transmits a J/K Start-of-Stream Delimiter
(SSD) symbol to the network. It then encodes and transmits the rest of the packet, including the
balance of the preamble, the Start-of-Frame Delimiter (SFD), packet data, and CRC. Once the
packet ends, the LXT9785/LXT9785E transmits the T/R End-of-Stream Delimiter (ESD) symbol
and then returns to transmitting Idle symbols.
100BASE-X Protocol Sublayer Operations
In a 7-layer communications model, the LXT9785/LXT9785E is a Physical Layer 1 (PHY) device.
The LXT9785/LXT9785E implements the Physical Coding Sublayer (PCS), Physical Medium
Attachment (PMA), and Physical Medium Dependent (PMD) sublayers of the reference model
defined by the IEEE 802.3u specification. The following paragraphs discuss the LXT9785/
LXT9785E operation from the reference model point of view.
PCS Sublayer
The Physical Coding Sublayer (PCS) provides the RMII interface, as well as the 4B/5B encoding/
decoding function. For 100BASE-TX and 100BASE-FX operation, the PCS layer provides IDLE
symbols to the PMD-layer line driver as long as TxEN is de-asserted. For 10T operation, the PCS
layer merely provides a bus interface and serialization/de-serialization function. 10T operation
does not use the 4B/5B encoder.
Replaced by
/J/K/ code-groups
Start-of-Stream
Delimiter (SSD)
P0
64-Bit Preamble
P1
(8 Octets)
Figure
P6
Delimiter (SFD)
Start-of-Frame
SFD
27, the MAC starts each transmission with a preamble pattern. As soon as the
Figure 27
DA
Address (6 Octets each)
Destination and Source
DA
shows the structure of a standard frame packet. When the MAC
SA
SA
Packet Length
L1
(2 Octets)
L2
(Pad to minimum packet size)
D0
Data Field
D1
Dn
Frame Check Field
(4 Octets)
CRC
End-of-Stream Delimiter (ESD)
Revision Date: 30-May-2006
Document Number: 249241
/T/R/ code-groups
Replaced by
InterFrame Gap / Idle Code
Revision Number: 010
I0
(> 12 Octets)
Datasheet
IFG