LULXT9785MBC.D0S L7WN Intel, LULXT9785MBC.D0S L7WN Datasheet - Page 92

• Manufacturer Part Number: LULXT9785MBC.D0S L7WN
• Manufacturer: Intel

Specifications of LULXT9785MBC.D0S L7WN

• Lead Free Status / RoHS Status: Compliant

Datasheet
Document Number: 249241
Revision Number: 010
Revision Date: 30-May-2006
Table 32. Miscellaneous Signal Descriptions – BGA23 (Sheet 4 of 4)
1. Type Column Coding: I = Input, O = Output, OD = Open Drain Output, ST = Schmitt Triggered Input, TS =
2. The IP/ID resistors are disabled during hardware power-down mode.
3. The LINKHOLD ability is available only for stepping 4 (Revision D0).
BGA23
A15
A12
A17
D7
Three-State-able Output, SL = Slew-rate Limited Output, IP = Weak Internal Pull-Up, ID = Weak Internal
Pull-Down.
Designation
Ball/Pin
PQFP
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
11
20
40
2
LINKHOLD
FIFOSEL1
FIFOSEL0
PREASEL
Symbol
3
I, ID, ST
I, ID, ST
I, ID, ST
Type
1
Signal Description
FIFO Select <1:0>.
These pins are read at startup or reset. Their value at
that time is used to set the default state of Register bits
18.15:14 for all ports. These register bits can be read
and overwritten after startup/reset.
These pins are shared with RMII-RxER<5:4>. An
external pull-up resistor (see applications section for
value) can be used to set FIFO Select<1:0> to active
while RxER<5:4> are three-stated during hardware
reset. If no pull-up is used, the default FIFO select
state is set via the internal pull-down resistors.
See
page
Preamble Select.
This pin is read at startup or reset. Its value at that time
is used to set the default state of Register bit 16.5 for
all ports. This register bit can be read and overwritten
after startup/reset.
This pin is shared with RMII-RxER2. An external pull-
up resistor (see applications section for value) can be
used to set Preamble Select to active while RxER2 is
three-stated during hardware reset. If no pull-up is
used, the default Preamble Select state is set via the
internal pull-down resistors.
Note: Preamble select has no effect in 100 Mbps
operation.
LINKHOLD Default. This pin is read at startup or
reset. Its value at that time is used to set the default
state of Register bit 0.11 for all ports. This register bit
can be read and overwritten after startup / reset. When
High, the LXT9785/9785E powers down all ports.
This pin is shared with RMII-RxER6. An external pull-
up resistor (see applications section for value) can be
used to set LINKHOLD active while RxER6 is tri-stated
during H/W reset. If no pull-up is used, the default
LINKHOLD state is set inactive via the internal pull-
down resistor.
Table 36 “Receive FIFO Depth Configurations” on
97.
2
92