PIC18F2221-E/ML Microchip Technology, PIC18F2221-E/ML Datasheet - Page 195

• Manufacturer Part Number: PIC18F2221-E/ML
• Description: 4KB, Flash, 512bytes-RAM, 25I/O, 8-bit Family,nanoWatt 28 QFN 6x6mm TUBE
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F2221-E/ML

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 25
• Program Memory Size: 4KB (2K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

18.4.6
Master mode is enabled by setting and clearing the
appropriate SSPM bits in SSPCON1 and by setting the
SSPEN bit. In Master mode, the SCL and SDA lines
are manipulated by the MSSP hardware.
Master mode of operation is supported by interrupt
generation on the detection of the Start and Stop
conditions. The Stop (P) and Start (S) bits are cleared
from a Reset or when the MSSP module is disabled.
Control of the I
set, or the bus is Idle, with both the S and P bits clear.
In Firmware Controlled Master mode, user code
conducts all I
Stop bit conditions.
Once Master mode is enabled, the user has six
options.
1.
2.
3.
4.
5.
6.
FIGURE 18-18:
© 2009 Microchip Technology Inc.
Assert a Start condition on SDA and SCL.
Assert a Repeated Start condition on SDA and
SCL.
Write
transmission of data/address.
Configure the I
Generate an Acknowledge condition at the end
of a received byte of data.
Generate a Stop condition on SDA and SCL.
SDA
SCL
MASTER MODE
to
2
C bus operations based on Start and
2
C bus may be taken when the P bit is
the
2
C port to receive data.
SSPBUF
MSSP BLOCK DIAGRAM (I
PIC18F2221/2321/4221/4321 FAMILY
SDA In
Bus Collision
SCL In
register
Read
initiating
MSb
Write Collision Detect
Start bit, Stop bit,
end of XMIT/RCV
State Counter for
Clock Arbitration
Acknowledge
Start bit Detect
Stop bit Detect
SSPBUF
Generate
SSPSR
2
C™ MASTER MODE)
LSb
Write
The following events will cause the MSSP Interrupt
Flag bit, SSPIF, to be set (MSSP interrupt, if enabled):
• Start condition
• Stop condition
• Data transfer byte transmitted/received
• Acknowledge transmit
• Repeated Start
Clock
Data Bus
Shift
Note:
Internal
Set/Reset, S, P, WCOL (SSPSTAT);
Set SSPIF, BCLIF;
Reset ACKSTAT, PEN (SSPCON2)
The MSSP module, when configured in
I
of events. For instance, the user is not
allowed to initiate a Start condition and
immediately write the SSPBUF register to
initiate transmission before the Start
condition is complete. In this case, the
SSPBUF will not be written to and the
WCOL bit will be set, indicating that a write
to the SSPBUF did not occur.
2
C Master mode, does not allow queueing
SSPADD<6:0>
SSPM<3:0>
Generator
Baud
Rate
DS39689F-page 195