PIC18F2221-E/ML Microchip Technology, PIC18F2221-E/ML Datasheet - Page 391

• Manufacturer Part Number: PIC18F2221-E/ML
• Description: 4KB, Flash, 512bytes-RAM, 25I/O, 8-bit Family,nanoWatt 28 QFN 6x6mm TUBE
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F2221-E/ML

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 25
• Program Memory Size: 4KB (2K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

DAW ................................................................................. 298
DC Characteristics ........................................................... 347
DCFSNZ .......................................................................... 299
DECF ............................................................................... 298
DECFSZ ........................................................................... 299
Development Support ...................................................... 329
Device Differences ........................................................... 386
Device Overview .................................................................. 9
Device Reset Timers .......................................................... 51
Direct Addressing ............................................................... 74
E
Effect on Standard PIC MCU Instructions ........................ 326
Effects of Power-Managed Modes on Various
Electrical Characteristics .................................................. 333
Enhanced Capture/Compare/PWM (ECCP) .................... 153
Enhanced PWM Mode. See PWM (ECCP Module). ........ 155
Enhanced Universal Synchronous Asynchronous Receiver
Equations
Errata ................................................................................... 8
EUSART
© 2009 Microchip Technology Inc.
Power-Down and Supply Current ............................ 337
Supply Voltage ......................................................... 336
Details on Individual Family Members ....................... 10
Features (table) .......................................................... 11
New Core Features ...................................................... 9
Other Special Features .............................................. 10
Oscillator Start-up Timer (OST) ................................. 51
PLL Lock Time-out ..................................................... 51
Power-up Timer (PWRT) ........................................... 51
Time-out Sequence .................................................... 51
Clock Sources ............................................................ 38
Associated Registers ............................................... 166
Capture and Compare Modes .................................. 154
Capture Mode. See Capture (ECCP Module).
Outputs and Configuration ....................................... 154
Pin Configurations for ECCP1 ................................. 154
PWM Mode. See PWM (ECCP Module).
Standard PWM Mode ............................................... 154
Timer Resources ...................................................... 154
A/D Acquisition Time ................................................ 238
A/D Minimum Charging Time ................................... 238
Calculating the Minimum Required
Asynchronous Mode ................................................ 221
Baud Rate Generator
Baud Rate Generator (BRG) .................................... 215
Transmitter (EUSART). See EUSART.
Acquisition Time .............................................. 238
12-Bit Break Transmit and Receive ................. 227
Associated Registers, Receive ........................ 225
Associated Registers, Transmit ....................... 223
Auto-Wake-up on Sync Break ......................... 226
Receiver ........................................................... 224
Setting up 9-Bit Mode with Address Detect ..... 224
Transmitter ....................................................... 221
Operation in Power-Managed Mode ................ 215
Associated Registers ....................................... 216
Auto-Baud Rate Detect .................................... 219
Baud Rate Error, Calculating ........................... 216
Baud Rates, Asynchronous Modes ................. 217
High Baud Rate Select (BRGH Bit) ................. 215
Sampling .......................................................... 215
PIC18F2221/2321/4221/4321 FAMILY
Extended Instruction Set
External Clock Input ........................................................... 30
F
Fail-Safe Clock Monitor ........................................... 259, 272
Fast Register Stack ........................................................... 62
Firmware Instructions ...................................................... 279
Flash Program Memory ..................................................... 79
FSCM. See Fail-Safe Clock Monitor.
G
GOTO .............................................................................. 300
H
Hardware Multiplier ............................................................ 95
Synchronous Master Mode ...................................... 228
Synchronous Slave Mode ........................................ 231
ADDFSR .................................................................. 322
ADDULNK ............................................................... 322
and Using MPLAB Tools ......................................... 328
CALLW .................................................................... 323
Considerations for Use ............................................ 326
MOVSF .................................................................... 323
MOVSS .................................................................... 324
PUSHL ..................................................................... 324
SUBFSR .................................................................. 325
SUBULNK ................................................................ 325
Syntax ...................................................................... 321
Exiting Operation ..................................................... 272
Interrupts in Power-Managed Modes ...................... 273
POR or Wake From Sleep ....................................... 273
WDT During Oscillator Failure ................................. 272
Associated Registers ................................................. 87
Control Registers ....................................................... 80
Erase Sequence ........................................................ 84
Erasing ...................................................................... 84
Operation During Code-Protect ................................. 87
Reading ..................................................................... 83
Table Pointer
Table Reads and Table Writes .................................. 79
Write Sequence ......................................................... 85
Writing ....................................................................... 85
Introduction ................................................................ 95
Operation ................................................................... 95
Performance Comparison .......................................... 95
Associated Registers, Receive ........................ 230
Associated Registers, Transmit ....................... 229
Reception ........................................................ 230
Transmission ................................................... 228
Associated Registers, Receive ........................ 232
Associated Registers, Transmit ....................... 231
Reception ........................................................ 232
Transmission ................................................... 231
EECON1 and EECON2 ..................................... 80
TABLAT (Table Latch) Register ........................ 82
TBLPTR (Table Pointer) Register ...................... 82
Boundaries ........................................................ 82
Boundaries Based on Operation ....................... 82
Operations with TBLRD and TBLWT (table) ..... 82
Protection Against Spurious Writes ................... 87
Unexpected Termination ................................... 87
Write Verify ........................................................ 87
DS39689F-page 391