PIC18F2221-E/ML Microchip Technology, PIC18F2221-E/ML Datasheet - Page 265
![4KB, Flash, 512bytes-RAM, 25I/O, 8-bit Family,nanoWatt 28 QFN 6x6mm TUBE](/photos/6/81/68120/150-28-qfn_sml.jpg)
PIC18F2221-E/ML
Manufacturer Part Number
PIC18F2221-E/ML
Description
4KB, Flash, 512bytes-RAM, 25I/O, 8-bit Family,nanoWatt 28 QFN 6x6mm TUBE
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC18F2221-ISO.pdf
(402 pages)
2.PIC18F2221-ISO.pdf
(8 pages)
3.PIC18F2221-ISO.pdf
(30 pages)
4.PIC18F2221-ISO.pdf
(46 pages)
Specifications of PIC18F2221-E/ML
Core Processor
PIC
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Number Of I /o
25
Program Memory Size
4KB (2K x 16)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 10x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
- PIC18F2221-ISO PDF datasheet
- PIC18F2221-ISO PDF datasheet #2
- PIC18F2221-ISO PDF datasheet #3
- PIC18F2221-ISO PDF datasheet #4
- Current page: 265 of 402
- Download datasheet (7Mb)
REGISTER 24-6:
REGISTER 24-7:
© 2009 Microchip Technology Inc.
bit 7
bit 6
bit 5-0
bit 7-2
bit 1
bit 0
CONFIG5L: CONFIGURATION REGISTER 5 LOW (BYTE ADDRESS 300008h)
CONFIG5H: CONFIGURATION REGISTER 5 HIGH (BYTE ADDRESS 300009h)
PIC18F2221/2321/4221/4321 FAMILY
CPD: Data EEPROM Code Protection bit
1 = Data EEPROM not code-protected
0 = Data EEPROM code-protected
CPB: Boot Block Code Protection bit
1 = Boot block not code-protected
0 = Boot block code-protected
Unimplemented: Read as ‘0’
bit 7
bit 7
Legend:
R = Readable bit
-n = Value when device is unprogrammed
Unimplemented: Read as ‘0’
CP1: Code Protection bit
1 = Block 1 not code-protected
0 = Block 1 code-protected
CP0: Code Protection bit
1 = Block 0 not code-protected
0 = Block 0 code-protected
Legend:
R = Readable bit
-n = Value when device is unprogrammed
Note 1: See Figure 24-5 for variable block boundaries.
R/C-1
Note 1: See Figure 24-5 for variable block boundaries.
CPD
U-0
—
R/C-1
CPB
U-0
—
C = Clearable bit
C = Clearable bit
(1)
(1)
U-0
U-0
—
—
(1)
(1)
(1)
(1)
U-0
U-0
—
—
U = Unimplemented bit, read as ‘0’
u = Unchanged from programmed state
U = Unimplemented bit, read as ‘0’
u = Unchanged from programmed state
U-0
U-0
—
—
U-0
U-0
—
—
R/C-1
CP1
U-0
—
DS39689F-page 265
R/C-1
CP0
U-0
—
bit 0
bit 0
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