SC68C752BIB48.128 NXP Semiconductors, SC68C752BIB48.128 Datasheet
SC68C752BIB48.128
Specifications of SC68C752BIB48.128
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SC68C752BIB48.128 Summary of contents
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SC68C752B 5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs and 68 mode μP interface Rev. 04 — 20 January 2010 1. General description The SC68C752B is a dual Universal Asynchronous Receiver/Transmitter (UART) with ...
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... NXP Semiconductors 5 V tolerant on input only pins Software selectable baud rate generator Prescaler provides additional divide-by-4 function Industrial temperature range (−40 °C to +85 °C) Fast data bus access time Programmable Sleep mode Programmable serial interface characteristics 5-bit, 6-bit, 7-bit, or 8-bit characters Even, odd parity bit generation and detection 1, 1 ...
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... NXP Semiconductors 4. Block diagram SC68C752B DATA BUS R/W CONTROL RESET REGISTER IRQ INTERRUPT TXRDYA, TXRDYB CONTROL RXRDYA, RXRDYB Fig 1. Block diagram of SC68C752B SC68C752B_4 Product data sheet 5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs AND LOGIC SELECT LOGIC ...
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... NXP Semiconductors 5. Pinning information 5.1 Pinning Fig 2. Fig 3. SC68C752B_4 Product data sheet 5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs RXB 4 RXA 5 6 TXRDYB SC68C752BIB48 7 TXA TXB 8 OPB n.c. Pin configuration for LQFP48 terminal 1 index area RXB 3 4 RXA ...
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... NXP Semiconductors 5.2 Pin description Table 2. Pin description Symbol Pin LQFP48 HVQFN32 CDA 40 - CDB CTSA 38 25 CTSB DSRA 39 - DSRB 20 - DTRA 34 - DTRB 35 - [1] GND 17 IRQ 30 21 SC68C752B_4 Product data sheet 5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs Type ...
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... NXP Semiconductors Table 2. Pin description …continued Symbol Pin LQFP48 HVQFN32 R n.c. 12, 25, 14, 20 29, 37 OPA 32 22 OPB 9 7 RESET 36 24 RIA 41 - RIB 21 - RTSA 33 23 RTSB 22 16 RXA 5 4 RXB 4 3 RXRDYA 31 - RXRDYB 18 - TXA 7 5 TXB 8 6 TXRDYA 43 - TXRDYB 19 XTAL1 13 10 XTAL2 ...
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... NXP Semiconductors [1] HVQFN32 package die supply ground is connected to both GND pin and exposed center pad. GND pin must be connected to supply ground for proper device operation. For enhanced thermal, electrical, and board level performance, the exposed pad needs to be soldered to the board using a corresponding thermal pad on the board and for proper heat conduction through the board, thermal vias need to be incorporated in the PCB in the thermal pad region ...
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... NXP Semiconductors If both auto-CTS and auto-RTS are enabled, when RTSn is connected to CTSn, data transmission does not occur unless the receive FIFO has empty space. Thus, overrun errors are eliminated during hardware flow control. If not enabled, overrun errors occur if the transmit data rate exceeds the receive FIFO servicing latency. ...
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... NXP Semiconductors 6.2.2 Auto-CTS The transmitter circuitry checks CTSn before sending the next data byte. When CTSn is active, the transmitter sends the next byte. To stop the transmitter from sending the following byte, CTSn must be de-asserted before the middle of the last stop bit that is currently being sent ...
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... NXP Semiconductors There are two other enhanced features relating to software flow control: • Xon Any function (MCR[5]): Operation will resume after receiving any character after recognizing the Xoff character possible that an Xon1 character is recognized as an Xon Any character, which could cause an Xon2 character to be written to the RX FIFO. • ...
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... NXP Semiconductors 6.3.3 Software flow control example Fig 7. 6.3.3.1 Assumptions UART1 is transmitting a large text file to UART2. Both UARTs are using software flow control with single character Xoff (0F) and Xon (0D) tokens. Both have Xoff threshold (TCR[3: set to 60, and Xon threshold (TCR[7: set to 32. Both have the interrupt receive threshold (TLR[7: set to 52 ...
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... NXP Semiconductors 6.4 Reset Table 5 Table 5. Register Interrupt Enable Register Interrupt Identification Register FIFO Control Register Line Control Register Modem Control Register Line Status Register Modem Status Register Enhanced Feature Register Receiver Holding Register Transmitter Holding Register Transmission Control Register Trigger Level Register Remark: Registers DLL, DLM, SPR, XON1, XON2, XOFF1, XOFF2 are not reset by the top-level reset signal RESET, that is, they hold their initialization values during reset ...
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... NXP Semiconductors 6.5 Interrupts The SC68C752B has interrupt generation and prioritization (six prioritized levels of interrupts) capability. The Interrupt Enable Register (IER) enables each of the six types of interrupts and the IRQ signal in response to an interrupt generation. The IER can also disable the interrupt system by clearing bits 3:0 and bits 7:5. When an interrupt is generated, the IIR indicates that an interrupt is pending and provides the type of interrupt through IIR[5:0] ...
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... NXP Semiconductors 6.5.1 Interrupt mode operation In Interrupt mode (if any bit of IER[3: the processor is informed of the status of the receiver and transmitter by an interrupt signal, IRQ. Therefore not necessary to continuously poll the Line Status Register (LSR) to see if any interrupt needs to be serviced. Fig 8. ...
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... NXP Semiconductors 6.6 DMA operation There are two modes of DMA operation, DMA mode 0 or DMA mode 1, selected by FCR[3]. In DMA mode 0 or FIFO disable (FCR[ DMA occurs in single character transfers. In DMA mode 1, multi-character (or block) DMA transfers are managed to relieve the processor for longer periods of time. ...
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... NXP Semiconductors 6.6.2 Block DMA transfers (DMA mode 1) Figure 11 trigger Fig 11. TXRDYn and RXRDYn in DMA mode 1 6.6.2.1 Transmitter TXRDYn is active when there is a trigger level number of spaces available. It becomes inactive when the FIFO is full. 6.6.2.2 Receiver RXRDYn becomes active when the trigger level has been reached, or when a time-out interrupt occurs ...
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... NXP Semiconductors 6.8 Break and time-out conditions An RX idle condition is detected when the receiver line, RXn, has been HIGH for 4 character time. The receiver line is sampled midway through each bit. When a break condition occurs, the TXn line is pulled LOW. A break condition is activated by setting LCR[6] ...
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... NXP Semiconductors Table 8. Desired baud rate 50 75 110 134.5 150 300 600 1200 1800 2000 2400 3600 4800 7200 9600 19200 38400 56000 Table 9. Desired baud rate 50 75 110 134.5 150 300 600 1200 1800 2000 2400 3600 4800 7200 9600 ...
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... NXP Semiconductors Fig 13. Crystal oscillator connections 7. Register descriptions Each register is selected using address lines A0, A1, A2, and in some cases, bits from other registers. The programming combinations for register selection are shown in Table 10. Table 10 [1] MCR[7] can only be modified when EFR[4] is set. [2] Accessed by a combination of address pins and register bits. ...
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... NXP Semiconductors Table 11 Table 11. SC68C752B internal registers Register Bit 7 [1] General register set RHR bit THR bit IER CTS interrupt [2] enable FCR RX trigger level (MSB IIR FCR[ LCR DLAB MCR 1× or 1×/4 [2] clock LSR error in RX FIFO MSR SPR ...
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... NXP Semiconductors Remark: Refer to the notes under 7.1 Receiver Holding Register (RHR) The receiver section consists of the Receiver Holding Register (RHR) and the Receiver Shift Register (RSR). The RHR is actually a 64-byte FIFO. The RSR receives serial data from the RX terminal. The data is converted to parallel data and moved to the RHR. The receiver section is controlled by the line control register ...
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... NXP Semiconductors 7.3 FIFO Control Register (FCR) This is a write-only register that is used for enabling the FIFOs, clearing the FIFOs, setting transmitter and receiver trigger levels, and selecting the type of DMA signalling. shows FIFO Control Register bit settings. Table 12. Bit 7:6 ...
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... NXP Semiconductors 7.4 Line Control Register (LCR) This register controls the data communication format. The word length, number of stop bits, and parity type are selected by writing the appropriate bits to the LCR. shows the Line Control Register bit settings. Table 13. Bit 1:0 ...
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... NXP Semiconductors 7.5 Line Status Register (LSR) Table 14 Table 14. Bit When the LSR is read, LSR[4:2] reflect the error bits (BI, FE, PE) of the character at the top of the receive FIFO (next character to be read). The LSR[4:2] registers do not physically exist, as the data read from the receive FIFO is output directly onto the output data bus, D[4:2], when the LSR is read ...
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... NXP Semiconductors Remark: The three error bits (parity, framing, break) may not be updated correctly in the first read of the LSR when the input clock (XTAL1) is running faster than 36 MHz. However, the second read is always correct strongly recommended that when using this device with a clock faster than 36 MHz, that the LSR be read twice and only the second read be used for decision making ...
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... NXP Semiconductors 7.7 Modem Status Register (MSR) This 8-bit register provides information about the current state of the control lines from the mode, data set, or peripheral device to the processor. It also indicates when a control input from the modem changes state. per channel. Table 16. ...
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... NXP Semiconductors 7.8 Interrupt Enable Register (IER) The Interrupt Enable Register (IER) enables each of the six types of interrupt, receiver error, RHR interrupt, THR interrupt, Xoff received, or CTSn/RTSn change of state from LOW to HIGH. The IRQ output signal is activated in response to interrupt generation. Table 17 Table 17 ...
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... NXP Semiconductors 7.9 Interrupt Identification Register (IIR) The IIR is a read-only 8-bit register which provides the source of the interrupt in a prioritized manner. Table 18. Bit Symbol 7:6 IIR[7:6] 5 IIR[5] 4 IIR[4] 3:1 IIR[3:1] 0 IIR[0] The interrupt priority list is shown in Table 19. Priority level SC68C752B_4 Product data sheet ...
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... NXP Semiconductors 7.10 Enhanced Feature Register (EFR) This 8-bit register enables or disables the enhanced features of the UART. shows the Enhanced Feature Register bit settings. Table 20. Bit Symbol 7 EFR[7] 6 EFR[6] 5 EFR[5] 4 EFR[4] 3:0 EFR[3:0] Combinations of software flow control can be selected by programming these 7 ...
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... NXP Semiconductors Remark: TCR can only be written to when EFR[ and MCR[ The programmer must program the TCR such that TCR[3:0] > TCR[7:4]. There is no built-in hardware check to make sure this condition is met. Also, the TCR must be programmed with this condition before auto-RTS or software flow control is enabled to avoid spurious operation of the device ...
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... NXP Semiconductors 8. Programmer’s guide The base set of registers that is used during high-speed data transfer have a straightforward access method. The extended function registers require special access bits to be decoded along with the address lines. The following guide will help with programming these registers. Note that the descriptions below are for individual register access ...
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... NXP Semiconductors Table 24. Command Set TX FIFO and RX FIFO thresholds to VALUE Read FIFO Rdy register Set prescaler value to divide-by-1 Set prescaler value to divide-by-4 × sign here means bit-AND. [1] SC68C752B_4 Product data sheet 5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs Register programming guide … ...
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... NXP Semiconductors 9. Limiting values Table 25. In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol amb T stg SC68C752B_4 Product data sheet 5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs Limiting values Parameter Conditions supply voltage voltage on any other pin ...
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... NXP Semiconductors 10. Static characteristics Table 26. Static characteristics ± Tolerance Symbol Parameter Conditions V supply voltage CC V input voltage I V HIGH-level IH input voltage V LOW-level input IL voltage V output voltage O = − HIGH-level output voltage = − −800 μ −400 μ LOW-level output voltage 1 input i capacitance T ambient ...
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... NXP Semiconductors 11. Dynamic characteristics Table 27. Dynamic characteristics − ° ° +85 C; tolerance of V amb Symbol Parameter t R/W to chip select d1 t read cycle delay d2 t delay from CS to data d3 t data disable time d4 t write cycle delay d6 t delay from WRITE to output ...
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... NXP Semiconductors 11.1 Timing diagrams su1 R Fig 14. General read timing su1 R Fig 15. General write timing SC68C752B_4 Product data sheet 5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs valid address valid data valid address su2 valid data Rev. 04 — 20 January 2010 ...
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... NXP Semiconductors (1) CS (write) RTSA, RTSB change of state DTRA, DTRB CDA, CDB CTSA, CTSB DSRA, DSRB IRQ (2) CS (read) RIA, RIB (1) CS timing during a write cycle. See (2) CS timing during a read cycle. See Fig 16. Modem input/output timing external clock 1 -------------- - f = XTAL1 ...
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... NXP Semiconductors RXA, RXB IRQ CS (read) Fig 18. Receive timing RXA, RXB RXRDYA, RXRDYB CS (read) Fig 19. Receive ready timing in non-FIFO mode SC68C752B_4 Product data sheet 5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs Start bit data bits ( data bits ...
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... NXP Semiconductors RXA, RXB RXRDYA, RXRDYB CS (read) Fig 20. Receive ready timing in FIFO mode TXA, TXB IRQ active CS (write) Fig 21. Transmit timing SC68C752B_4 Product data sheet 5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs Start bit data bits ( Start ...
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... NXP Semiconductors TXA, TXB CS (write) active byte #1 TXRDYA, TXRDYB Fig 22. Transmit ready timing in non-FIFO mode TXA, TXB CS (write) active byte #64 TXRDYA, TXRDYB Fig 23. Transmit ready timing in FIFO mode SC68C752B_4 Product data sheet 5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs ...
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... NXP Semiconductors 12. Package outline LQFP48: plastic low profile quad flat package; 48 leads; body 1 pin 1 index DIMENSIONS (mm are the original dimensions) A UNIT max. 0.20 1.45 1.6 mm 0.25 0.05 1.35 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION ...
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... NXP Semiconductors HVQFN32: plastic thermal enhanced very thin quad flat package; no leads; 32 terminals; body 0.85 mm terminal 1 index area terminal 1 index area 32 DIMENSIONS (mm are the original dimensions) (1) A UNIT max. 0.05 0. 0.2 0.00 0.18 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. ...
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... NXP Semiconductors 13. Soldering of SMD packages This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “Surface mount reflow soldering description”. 13.1 Introduction to soldering Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits ...
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... NXP Semiconductors 13.4 Reflow soldering Key characteristics in reflow soldering are: • Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see reducing the process window • Solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board • ...
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... NXP Semiconductors Fig 26. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description”. 14. Abbreviations Table 30. Acronym CPU DMA FIFO LSB MSB PCB TTL UART SC68C752B_4 Product data sheet 5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs ...
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... Modifications: The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. • Legal texts have been adapted to the new company name where appropriate. • Descriptive title of data sheet modified: changed from “Motorola” to “68 mode” ...
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... Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice ...
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... NXP Semiconductors 18. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 4 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 5 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 6 Functional description . . . . . . . . . . . . . . . . . . . 7 6.1 Trigger levels . . . . . . . . . . . . . . . . . . . . . . . . . . 7 6.2 Hardware flow control . . . . . . . . . . . . . . . . . . . . 7 6.2.1 Auto-RTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 6.2.2 Auto-CTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 6.3 Software flow control . . . . . . . . . . . . . . . . . . . . 9 6.3.1 Receive flow control . . . . . . . . . . . . . . . . . . . . 10 6 ...