SC68C752BIB48.128 NXP Semiconductors, SC68C752BIB48.128 Datasheet - Page 46

• Manufacturer Part Number: SC68C752BIB48.128
• Manufacturer: NXP Semiconductors

Specifications of SC68C752BIB48.128

• Transmit Fifo: 64Byte
• Receive Fifo: 64Byte
• Transmitter And Receiver Fifo Counter: Yes
• Data Rate: 5Mbps
• Package Type: LQFP
• Operating Supply Voltage (max): 5.5V
• Mounting: Surface Mount
• Pin Count: 48
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Industrial
• Number Of Channels: 2
• Lead Free Status / RoHS Status: Compliant

NXP Semiconductors
15. Revision history
Table 31.
SC68C752B_4
Product data sheet
Document ID
SC68C752B_4
Modifications:
SC68C752B_3
SC68C752B_2
(9397 750 14963)
SC68C752B_1
(9397 750 13857)
Revision history
Release date
20100120
20051129
20050428
20050329
•
•
•
•
•
•
•
•
•
•
The format of this data sheet has been redesigned to comply with the new identity guidelines of
NXP Semiconductors.
Legal texts have been adapted to the new company name where appropriate.
Descriptive title of data sheet modified: changed from “Motorola” to “68 mode”
Section 2
– 1
– 10
– 10
Table 2 “Pin
Section 7.11 “Divisor latches (DLL,
sheet)
Table 25 “Limiting
– removed specification for V
– added specification for V
– removed table note [1] and its reference (statement is now covered in
Table 26 “Static
mode supply current”
Table 27 “Dynamic
– added
– split symbol/parameter “t
– denominator in equation in
Figure 17 “External clock
– changed symbol from “t
– changed symbol from “t
– changed symbol from “t
width HIGH” and “t
st
th
th
bullet item changed from “Motorola μP interface” to “68 mode (Motorola) μP interface”
bullet item changed from “5 V tolerant inputs” to “5 V tolerant on input only pins”
bullet item added
“Features”:
Table note [4]
description”: added
Data sheet status
Product data sheet
characteristics”: parameter for I
Product data sheet
Product data sheet
Product data sheet
values”:
characteristics”:
5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs
WL
Rev. 04 — 20 January 2010
and its reference at t
, pulse width LOW”
Footnote 1
timing”:
w1
w2
w3
n
w1
” to “t
” to “t
” to “t
, t
I
Table note [3]
w2
Table note [1]
, clock cycle period” to two symbol/parameters, “t
WH
WL
w(clk)
DLM)”: changed from “DLH” to “DLM” (and throughout data
”
”
” (in both drawing and equation denominator)
changed from “t
(RESET)
and its reference at HVQFN32 pin 13.
CC(sleep)
Change notice
-
-
-
-
changed from “sleep current” to “sleep
w3
” to “t
w(clk)
SC68C752B
Supersedes
SC68C752B_3
SC68C752B_2
SC68C752B_1
-
”
Section
© NXP B.V. 2010. All rights reserved.
16.3)
WH
, pulse
46 of 48