SC68C752BIB48.128 NXP Semiconductors, SC68C752BIB48.128 Datasheet - Page 14

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SC68C752BIB48.128

Manufacturer Part Number
SC68C752BIB48.128
Description
Manufacturer
NXP Semiconductors
Datasheet

Specifications of SC68C752BIB48.128

Transmit Fifo
64Byte
Receive Fifo
64Byte
Transmitter And Receiver Fifo Counter
Yes
Data Rate
5Mbps
Package Type
LQFP
Operating Supply Voltage (max)
5.5V
Mounting
Surface Mount
Pin Count
48
Operating Temperature (min)
-40C
Operating Temperature (max)
85C
Operating Temperature Classification
Industrial
Number Of Channels
2
Lead Free Status / RoHS Status
Compliant
NXP Semiconductors
SC68C752B_4
Product data sheet
6.5.1 Interrupt mode operation
6.5.2 Polled mode operation
In Interrupt mode (if any bit of IER[3:0] is 1) the processor is informed of the status of the
receiver and transmitter by an interrupt signal, IRQ. Therefore, it is not necessary to
continuously poll the Line Status Register (LSR) to see if any interrupt needs to be
serviced.
In Polled mode (IER[3:0] = 0000) the status of the receiver and transmitter can be
checked by polling the Line Status Register (LSR). This mode is an alternative to the FIFO
Interrupt mode of operation where the status of the receiver and transmitter is
automatically known by means of interrupts sent to the CPU.
polled mode operation.
Fig 8.
Fig 9.
Interrupt mode operation
FIFO polled mode operation
Figure 8
PROCESSOR
PROCESSOR
shows Interrupt mode operation.
5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs
Rev. 04 — 20 January 2010
R/W
R/W
IRQ
THR
THR
IER
IER
IIR
IIR
Figure 9
1
0
SC68C752B
1
0
RHR
RHR
1
002aab096
0
002aab097
shows FIFO
1
0
© NXP B.V. 2010. All rights reserved.
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