SC68C752BIB48.128 NXP Semiconductors, SC68C752BIB48.128 Datasheet - Page 20

• Manufacturer Part Number: SC68C752BIB48.128
• Manufacturer: NXP Semiconductors

Specifications of SC68C752BIB48.128

• Transmit Fifo: 64Byte
• Receive Fifo: 64Byte
• Transmitter And Receiver Fifo Counter: Yes
• Data Rate: 5Mbps
• Package Type: LQFP
• Operating Supply Voltage (max): 5.5V
• Mounting: Surface Mount
• Pin Count: 48
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Industrial
• Number Of Channels: 2
• Lead Free Status / RoHS Status: Compliant

NXP Semiconductors
Table 11.
[1]
[2]
[3]
[4]
SC68C752B_4
Product data sheet
A2 A1 A0 Register Bit 7
General register set
0
0
0
0
0
0
1
1
1
1
1
1
1
Special register set
0
0
Enhanced register set
0
1
1
1
1
These registers are accessible only when LCR[7] = 0.
This bit can only be modified if register bit EFR[4] is enabled, that is, if enhanced functions are enabled.
The Special register set is accessible only when LCR[7] is set to a logic 1.
Enhanced Feature Register; XON1/XON2 and XOFF1/XOFF2 are accessible only when LCR is set to ‘BFh’.
0
0
0
1
1
1
0
0
1
1
1
1
1
0
0
1
0
0
1
1
0
0
1
0
0
1
0
1
0
1
0
1
1
0
1
0
0
1
0
1
SC68C752B internal registers
RHR
THR
IER
FCR
IIR
LCR
MCR
LSR
MSR
SPR
TCR
TLR
FIFO Rdy 0
DLL
DLM
EFR
XON1
XON2
XOFF1
XOFF2
[3]
[1]
[4]
Table 11
bit 7
bit 7
CTS
interrupt
enable
RX trigger
level
(MSB)
FCR[0]
DLAB
1× or 1×/4
clock
error in
RX FIFO
CD
bit 7
bit 7
bit 7
bit 7
bit 15
auto-CTS auto-RTS special
bit 7
bit 7
bit 7
bit 7
[2]
[2]
lists and describes the SC68C752B internal registers.
Bit 6
bit 6
bit 6
RTS
interrupt
enable
RX trigger
level
(LSB)
FCR[0]
break
control bit
TCR and
TLR
enable
THR and
TSR
empty
RI
bit 6
bit 6
bit 6
0
bit 6
bit 14
bit 6
bit 6
bit 6
bit 6
[2]
[2]
5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs
Bit 5
bit 5
bit 5
Xoff
TX trigger
level
(MSB)
CTS,
RTS
set parity parity
Xon
Any
THR
empty
DSR
bit 5
bit 5
bit 5
RX FIFO
B status
bit 5
bit 13
character
detect
bit 5
bit 5
bit 5
bit 5
Rev. 04 — 20 January 2010
[2]
[2]
[2]
bit 4
CTS
bit 4
bit 4
Bit 4
bit 4
Sleep
mode
TX trigger
level
(LSB)
Xoff
type
select
enable
loopback
break
interrupt
bit 4
bit 4
bit 4
RX FIFO
A status
bit 4
bit 12
enable
enhanced
functions
[2]
bit 4
bit 4
[2]
[2]
Bit 3
bit 3
bit 3
modem
status
interrupt
DMA
mode
select
interrupt
priority
bit 2
parity
enable
OPA/
OPB
control
framing
error
ΔCD
bit 3
bit 3
bit 3
0
bit 3
bit 11
software
flow
control
bit 3
bit 3
bit 3
bit 3
bit 3
Bit 2
bit 2
bit 2
receive
line status
interrupt
TX FIFO
reset
interrupt
priority
bit 1
number of
stop bits
FIFO
ready
enable
parity
error
ΔRI
bit 2
bit 2
bit 2
0
bit 2
bit 10
software
flow
control
bit 2
bit 2
bit 2
bit 2
bit 2
Bit 1
bit 1
bit 1
THR
empty
interrupt
RX FIFO
reset
interrupt
priority
bit 0
word
length
bit 1
RTS
overrun
error
ΔDSR
bit 1
bit 1
bit 1
TX FIFO
B status
bit 1
bit 9
software
flow
control
bit 1
bit 1
bit 1
bit 1
bit 1
SC68C752B
© NXP B.V. 2010. All rights reserved.
Bit 0
bit 0
bit 0
RX data
available
interrupt
FIFO
enable
interrupt
status
word
length
bit 0
DTR
data in
receiver
ΔCTS
bit 0
bit 0
bit 0
TX FIFO
A status
bit 0
bit 8
software
flow
control
bit 0
bit 0
bit 0
bit 0
bit 0
20 of 48
Read/
Write
R
W
R/W
W
R
R/W
R/W
R
R
R/W
R/W
R/W
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W