SC68C752BIB48.128 NXP Semiconductors, SC68C752BIB48.128 Datasheet - Page 24

• Manufacturer Part Number: SC68C752BIB48.128
• Manufacturer: NXP Semiconductors

Specifications of SC68C752BIB48.128

• Transmit Fifo: 64Byte
• Receive Fifo: 64Byte
• Transmitter And Receiver Fifo Counter: Yes
• Data Rate: 5Mbps
• Package Type: LQFP
• Operating Supply Voltage (max): 5.5V
• Mounting: Surface Mount
• Pin Count: 48
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Industrial
• Number Of Channels: 2
• Lead Free Status / RoHS Status: Compliant

NXP Semiconductors
SC68C752B_4
Product data sheet
7.5 Line Status Register (LSR)
Table 14
Table 14.
When the LSR is read, LSR[4:2] reflect the error bits (BI, FE, PE) of the character at the
top of the receive FIFO (next character to be read). The LSR[4:2] registers do not
physically exist, as the data read from the receive FIFO is output directly onto the output
data bus, D[4:2], when the LSR is read. Therefore, errors in a character are identified by
reading the LSR and then reading the RHR.
LSR[7] is set when there is an error anywhere in the receive FIFO, and is cleared only
when there are no more errors remaining in the FIFO.
Reading the LSR does not cause an increment of the receive FIFO read pointer. The
receive FIFO read pointer is incremented by reading the RHR.
Bit
7
6
5
4
3
2
1
0
Symbol
LSR[7]
LSR[6]
LSR[5]
LSR[4]
LSR[3]
LSR[2]
LSR[1]
LSR[0]
shows the Line Status Register bit settings.
Line Status Register bits description
Description
FIFO data error.
THR and TSR empty. This bit is the Transmit Empty indicator.
THR empty. This bit is the Transmit Holding Register Empty indicator.
Break interrupt.
Framing error.
Parity error.
Overrun error.
Data in receiver.
5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs
logic 0 = No error (normal default condition)
logic 1 = At least one parity error, framing error, or break indication is in the
receiver FIFO. This bit is cleared when no more errors are present in the
FIFO.
logic 0 = transmitter hold and shift registers are not empty
logic 1 = transmitter hold and shift registers are empty
logic 0 = Transmit Hold Register is not empty
logic 1 = Transmit Hold Register is empty. The processor can now load up to
64 bytes of data into the THR if the TX FIFO is enabled.
logic 0 = no break condition (normal default condition)
logic 1 = A break condition occurred and associated byte is 00, that is,
RXn was LOW for one character time frame.
logic 0 = no framing error in data being read from receive FIFO (normal
default condition)
logic 1 = Framing error occurred in data being read from receive FIFO,
that is, received data did not have a valid stop bit.
logic 0 = no parity error (normal default condition)
logic 1 = parity error in data being read from receive FIFO
logic 0 = no overrun error (normal default condition)
logic 1 = overrun error has occurred
logic 0 = no data in receive FIFO (normal default condition)
logic 1 = at least one character in the receive FIFO
Rev. 04 — 20 January 2010
SC68C752B
© NXP B.V. 2010. All rights reserved.
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