SC68C752BIB48.128 NXP Semiconductors, SC68C752BIB48.128 Datasheet - Page 5

• Manufacturer Part Number: SC68C752BIB48.128
• Manufacturer: NXP Semiconductors

Specifications of SC68C752BIB48.128

• Transmit Fifo: 64Byte
• Receive Fifo: 64Byte
• Transmitter And Receiver Fifo Counter: Yes
• Data Rate: 5Mbps
• Package Type: LQFP
• Operating Supply Voltage (max): 5.5V
• Mounting: Surface Mount
• Pin Count: 48
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Industrial
• Number Of Channels: 2
• Lead Free Status / RoHS Status: Compliant

NXP Semiconductors
Table 2.
SC68C752B_4
Product data sheet
Symbol
A0
A1
A2
A3
CDA
CDB
CS
CTSA
CTSB
D0
D1
D2
D3
D4
D5
D6
D7
DSRA
DSRB
DTRA
DTRB
GND
IRQ
Pin description
Pin
LQFP48 HVQFN32
28
27
26
11
40
16
10
38
23
44
45
46
47
48
1
2
3
39
20
34
35
17, 24
30
5.2 Pin description
19
18
17
9
-
-
8
25
15
27
28
29
30
31
32
1
2
-
-
-
-
13
21
[1]
Type
I
I
I
I
I
I
I
I
I
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
I
O
O
I
O
Description
Address 0 select bit. Internal registers address selection.
Address 1 select bit. Internal registers address selection.
Address 2 select bit. Internal registers address selection.
Address 3. A3 is used to select Channel A or Channel B. A logic LOW selects
Channel A, and a logic HIGH selects Channel B. (See
Carrier Detect (active LOW). These inputs are associated with individual UART
Channel A and Channel B. A logic LOW on these pins indicates that a carrier has
been detected by the modem for that channel. The state of these inputs is
reflected in the Modem Status Register (MSR).
Chip Select (active LOW). This pin enables data transfers between the user
CPU and the SC68C752B for the channel(s) addressed. Individual UART
sections (A, B) are addressed by A3. See
Clear to Send (active LOW). These inputs are associated with individual UART
Channel A and Channel B. A logic 0 (LOW) on the CTSn pins indicates the
modem or data set is ready to accept transmit data from the SC68C752B. Status
can be tested by reading MSR[4]. These pins only affect the transmit and receive
operations when auto-CTS function is enabled via the Enhanced Feature
Register EFR[7] for hardware flow control operation.
Data bus (bidirectional). These pins are the 8-bit, 3-state data bus for
transferring information to or from the controlling CPU. D0 is the least significant
bit and the first data bit in a transmit or receive serial data stream.
Data Set Ready (active LOW). These inputs are associated with individual
UART Channel A and Channel B. A logic 0 (LOW) on these pins indicates the
modem or data set is powered-on and is ready for data exchange with the UART.
The state of these inputs is reflected in the Modem Status Register (MSR).
Data Terminal Ready (active LOW). These outputs are associated with
individual UART Channel A and Channel B. A logic 0 (LOW) on these pins
indicates that the SC68C752B is powered-on and ready. These pins can be
controlled via the Modem Control Register. Writing a logic 1 to MCR[0] will set the
DTRn output pin to logic 0 (LOW), enabling the modem. The output of these pins
will be a logic 1 after writing a logic 0 to MCR[0], or after a reset.
Signal and power ground.
Interrupt Request. Interrupts from UART Channel A and Channel B are
wire-ORed internally to function as a single IRQ interrupt. This pin transitions to a
logic 0 (if enabled by the Interrupt Enable Register) whenever a UART channel(s)
requires service. Individual channel interrupt status can be determined by
addressing each channel through its associated internal register, using CS and
A3. An external pull-up resistor must be connected between this pin and V
5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs
Rev. 04 — 20 January 2010
Table
3.
SC68C752B
Table
3.)
© NXP B.V. 2010. All rights reserved.
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