ISP1109BS,118 NXP Semiconductors, ISP1109BS,118 Datasheet - Page 56

• Manufacturer Part Number: ISP1109BS,118
• Description: RF Transceiver USB FS TRANSCVR
• Manufacturer: NXP Semiconductors

Specifications of ISP1109BS,118

• Number Of Transceivers: 1
• Esd Protection: YeskV
• Power Supply Requirement: Triple
• Operating Supply Voltage (typ): Not RequiredV
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (max): Not RequiredV
• Operating Supply Voltage (min): Not RequiredV
• Pin Count: 32
• Mounting: Surface Mount
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Operating Supply Voltage: 1.65 V to 5.25 V
• Lead Free Status / RoHS Status: Compliant
• Other names: 935276024118 ISP1109BS-T

Philips Semiconductors
28. Tables
Table 1:
Table 2:
Table 3:
Table 4:
Table 5:
Table 6:
Table 7:
Table 8:
Table 9:
Table 10: ISP1109 power modes: summary . . . . . . . . . .16
Table 11: ISP1109 pin states in disable or isolate mode .16
Table 12: USB functional modes: I/O values . . . . . . . . . .17
Table 13: Summary of device operating modes . . . . . . .18
Table 14: Transparent general-purpose buffer mode . . . .19
Table 15: Register overview . . . . . . . . . . . . . . . . . . . . . .20
Table 16: VENDORID - Vendor ID register (address
Table 17: PRODUCTID - Product ID register (address
Table 18: VERSIONID - Version ID register (address
Table 19: Mode Control 1 register (address Set = 04h,
Table 20: Mode Control 1 register (address Set = 04h,
Table 21: Mode Control 2 register (address Set = 12h,
Table 22: Mode Control 2 register (address Set = 12h,
Table 23: Audio Control register (address Set = 16h,
Table 24: Audio Control register (address Set = 16h,
Table 25: Timer Control register (address Set = 18h,
Table 26: Timer Control register (address Set = 18h,
Table 27: Resistor Control register (address Set = 06h,
Table 28: Resistor Control register (address Set = 06h,
Table 29: Interrupt Source register (address 08h) bit
Table 30: Interrupt Source register (address 08h) bit
Table 31: Interrupt Latch register (address Set = 0Ah,
Table 32: Interrupt Latch register (address Set = 0Ah,
9397 750 13355
Product data sheet
Ordering information . . . . . . . . . . . . . . . . . . . . .2
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . .5
ID pull-down control . . . . . . . . . . . . . . . . . . . . . .9
DP pull-up resistor (R
Audio switch control . . . . . . . . . . . . . . . . . . . . .11
Transceiver driver operating setting . . . . . . . . .12
USB functional mode: transmit operation . . . .12
Differential receiver operation settings . . . . . . .13
USB functional mode: receive operation . . . . .13
00h to 01h) bit description . . . . . . . . . . . . . . . .20
02h to 03h) bit description . . . . . . . . . . . . . . . .21
14h to 15h) bit description . . . . . . . . . . . . . . . .21
Clear = 05h) bit allocation . . . . . . . . . . . . . . . .21
Clear = 05h) bit description . . . . . . . . . . . . . . .21
Clear = 13h) bit allocation . . . . . . . . . . . . . . . .22
Clear = 13h) bit description . . . . . . . . . . . . . . .22
Clear = 17h) bit allocation . . . . . . . . . . . . . . . .22
Clear = 17h) bit description . . . . . . . . . . . . . . .22
Clear = 19h) bit allocation . . . . . . . . . . . . . . . .23
Clear = 19h) bit description . . . . . . . . . . . . . . .23
Clear = 07h) bit allocation . . . . . . . . . . . . . . . .23
Clear = 07h) bit description . . . . . . . . . . . . . . .24
allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
Clear = 0Bh) bit allocation . . . . . . . . . . . . . . . .25
UP(DP)
) control . . . . . . . . .9
Rev. 01 — 14 July 2005
Table 33: Interrupt Enable Low register (address
Table 34: Interrupt Enable Low register (address
Table 35: Interrupt Enable High register (address
Table 36: Interrupt Enable High register (address
Table 37: SPI interface pin description . . . . . . . . . . . . . . 28
Table 38: I
Table 39: I
Table 40: I
Table 41: Transfer format description for a one-byte
Table 42: Transfer format description for a multiple-byte
Table 43: Transfer format description for current address
Table 44: Transfer format description for single-byte
Table 45: Transfer format description for a multiple-
Table 46: Limiting values . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 47: Recommended operating conditions . . . . . . . . 36
Table 48: Static characteristics: supply pins . . . . . . . . . . 37
Table 49: Static characteristics: digital pins (except
Table 50: Static characteristics: digital pin ISET . . . . . . . 38
Table 51: Static characteristics: analog I/O pins DP
Table 52: Static characteristics: analog I/O pins ID
Table 53: Static characteristics: analog I/O pin V
Table 54: Static characteristics: analog I/O pins
Table 55: Dynamic characteristics: reset and clock . . . . 40
Table 56: Dynamic characteristics: bus turnaround
Table 57: Dynamic characteristics: analog I/O pins DP
Table 58: Dynamic characteristics: analog I/O pin ID . . . 41
Table 59: Dynamic characteristics: audio switches . . . . . 41
Table 60: SPI timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Table 61: Characteristics of I/O stages of I
Table 62: Test configurations . . . . . . . . . . . . . . . . . . . . . 46
Clear = 0Bh) bit description . . . . . . . . . . . . . . . 25
Set = 0Ch, Clear = 0Dh) bit allocation . . . . . . . 26
Set = 0Ch, Clear = 0Dh) bit description . . . . . 26
Set = 0Eh, Clear = 0Fh) bit allocation . . . . . . . 27
Set = 0Eh, Clear = 0Fh) bit description . . . . . . 27
write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
byte read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
for ISET) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
and
DM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
and ID_PU . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
SPKR_L, SPKR_R and MIC . . . . . . . . . . . . . . 39
timing (USB bidirectional mode) . . . . . . . . . . . 40
and DM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
(SDA, SCL) . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
2
2
2
C-bus byte transfer format . . . . . . . . . . . . . . 29
C-bus slave address bit allocation . . . . . . . . 30
C-bus slave address bit description . . . . . . . 30
USB transceiver with carkit support
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
ISP1109
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