SAA7105E/V1/G NXP Semiconductors, SAA7105E/V1/G Datasheet - Page 13

• Manufacturer Part Number: SAA7105E/V1/G
• Description: Video ICs PC-DENC
• Manufacturer: NXP Semiconductors

Specifications of SAA7105E/V1/G

• Adc/dac Resolution: 10b
• Screening Level: Commercial
• Package Type: LBGA
• Pin Count: 156
• Lead Free Status / RoHS Status: Compliant
• Other names: SAA7105E/V1/G,557

Philips Semiconductors
SAA7104E_SAA7105E_2
Product data sheet
7.12.1 Video path
7.10 Oscillator and Discrete Time Oscillator (DTO)
7.11 Low-pass Clock Generation Circuit (CGC)
7.12 Encoder
The master clock generation is realized as a 27 MHz crystal oscillator, which can operate
with either a fundamental wave crystal or a 3rd-harmonic crystal.
The crystal clock supplies the DTO of the pixel clock synthesizer, the video encoder and
the I
auxiliary VGA or HDTV mode, where the triple DAC is clocked by the pixel clock
(PIXCLK).
The DTO can be programmed to synthesize all relevant pixel clock frequencies between
circa 40 MHz and 85 MHz. Two programmable dividers provide the actual clock to be
used externally and internally. The dividers can be programmed to factors of 1, 2, 4 and 8.
For the internal pixel clock, a divider ratio of 8 makes no sense and is thus forbidden.
The internal clock can be switched completely to the pixel clock input. In this event, the
input FIFO is useless and will be bypassed.
The entire pixel clock generation can be locked to the vertical frequency. Both pixel clock
dividers get re-initialized every field. Optionally, the DTO can be cleared with each V-sync.
At proper programming, this will make the pixel clock frequency a precise multiple of the
vertical and horizontal frequencies. This is required for some graphic controllers.
This block reduces the phase jitter of the synthesized pixel clock. It works as a tracking
filter for all relevant synthesized pixel clock frequencies.
The encoder generates luminance and color subcarrier output signals from the Y,
C
signals.
Input to the encoder, at 27 MHz clock (e.g. DVD), is either originated from computer
graphics at pixel clock, fed through the FIFO and border generator, or a ITU-R BT.656
style signal.
Luminance is modified in gain and in offset (the offset is programmable in a certain range
to enable different black level set-ups). A blanking level can be set after insertion of a fixed
synchronization pulse tip level, in accordance with standard composite synchronization
schemes. Other manipulations used for the Macrovision anti-taping process, such as
additional insertion of AGC super-white pulses (programmable in height), are supported
by the SAA7104E only.
To enable easy analog post filtering, luminance is interpolated from a 13.5 MHz data rate
to a 27 MHz data rate, thereby providing luminance in a 10-bit resolution. The transfer
characteristics of the luminance interpolation filter are illustrated in
Appropriate transients at start/end of active video and for synchronization pulses are
ensured.
B
and C
2
C-bus control block. It also usually supplies the triple DAC, with the exception of the
R
baseband signals, which are suitable for use as CVBS or separate Y and C
Rev. 02 — 23 December 2005
SAA7104E; SAA7105E
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Digital video encoder
Figure 8
and
Figure
13 of 78
9.