SAA7105E/V1/G NXP Semiconductors, SAA7105E/V1/G Datasheet - Page 35

• Manufacturer Part Number: SAA7105E/V1/G
• Description: Video ICs PC-DENC
• Manufacturer: NXP Semiconductors

Specifications of SAA7105E/V1/G

• Adc/dac Resolution: 10b
• Screening Level: Commercial
• Package Type: LBGA
• Pin Count: 156
• Lead Free Status / RoHS Status: Compliant
• Other names: SAA7105E/V1/G,557

Philips Semiconductors
SAA7104E_SAA7105E_2
Product data sheet
Table 25:
Legend: * = default value after reset.
Table 26:
Legend: * = default value after reset.
Table 27:
Legend: * = default value after reset.
Subaddress Bit
27h
26h
Bit
7 and 6 -
5 to 0
Bit
7
6
5 to 0
Symbol Access Value Description
BS[5:0]
Symbol Access Value Description
SRES
-
BE[5:0]
Wide screen signal registers, subaddresses 26h and 27h, bit description
Real-time control and burst start register, subaddress 28h, bit description
Sync reset enable and burst end register, subaddress 29h, bit description
7
6
5 to 3 WSS[13:11] R/W
2 to 0 WSS[10:8]
7 to 4 WSS[7:4]
3 to 0 WSS[3:0]
R/W
R/W
R/W
R/W
R/W
Symbol
WSSON
-
Rev. 02 — 23 December 2005
0
21h*
19h*
0*
1
0
1Dh*
1Dh*
Access Value Description
R/W
R/W
R/W
R/W
R/W
must be programmed with logic 0 to ensure compatibility to
future enhancements
starting point of burst in clock cycles
PAL: BS = 33; strapping pin FSVGC tied to HIGH
NTSC: BS = 25; strapping pin FSVGC tied to LOW
pin TTX_SRES accepts a teletext bit stream (TTX)
pin TTX_SRES accepts a sync reset input (SRES); a HIGH
impulse resets synchronization of the encoder (first field, first
line)
must be programmed with logic 0 to ensure compatibility to
future enhancements
ending point of burst in clock cycles
PAL: BE = 29; strapping pin FSVGC tied to HIGH
NTSC: BE = 29; strapping pin FSVGC tied to LOW
0*
1
0
-
-
-
-
SAA7104E; SAA7105E
wide screen signalling output is disabled
wide screen signalling output is enabled
must be programmed with logic 0 to ensure
compatibility to future enhancements
wide screen signalling bits, reserved
wide screen signalling bits, subtitles
wide screen signalling bits, enhanced
services
wide screen signalling bits, aspect ratio
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Digital video encoder
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