SAA7105E/V1/G NXP Semiconductors, SAA7105E/V1/G Datasheet - Page 7

• Manufacturer Part Number: SAA7105E/V1/G
• Description: Video ICs PC-DENC
• Manufacturer: NXP Semiconductors

Specifications of SAA7105E/V1/G

• Adc/dac Resolution: 10b
• Screening Level: Commercial
• Package Type: LBGA
• Pin Count: 156
• Lead Free Status / RoHS Status: Compliant
• Other names: SAA7105E/V1/G,557

Philips Semiconductors
SAA7104E_SAA7105E_2
Product data sheet
Table 4:
[1]
[2]
[3]
[4]
[5]
[6]
Symbol
GREEN_VBS_CVBS C7
RED_CR_C_CVBS
TDO
RESET
TMS
V
V
V
V
VSM
HSM_CSYNC
TCK
SCL
HSVGC
reserved
VSVGC
PIXCLKI
PD3
V
TVD
FSVGC
SDA
CBO
PIXCLKO
PD2
PD1
PD0
DDD2
DDD3
DDD4
DDA3
DDD1
Pin type: I = input, O = output, S = supply, pu = pull-up.
See
In accordance with the ‘IEEE1149.1’ standard the pins TDI, TMS, TCK and TRST are input pins with an
internal pull-up resistor and TDO is a 3-state output pin.
For board design without boundary scan implementation connect TRST to ground.
This pin provides easy initialization of the BST circuit. TRST can be used to force the Test Access Port
(TAP) controller to the TEST_LOGIC_RESET state (normal operation) at once.
Pins FSVGC, VSVGC, CBO, HSVGC and TTXRQ_XCLKO2 are used for bootstrapping; see
Table 12
Pin description
to
Table 18
Rev. 02 — 23 December 2005
Pin
C8
D1
D2
D3
D4
D4
D4
D6
D7
D8
E1
E2
E3
E12
F1
F2
F3
F4
F12
G1
G2
G3
G4
H1
H2
H3
for pin assignment.
…continued
Type
O
O
O
I
I/pu
S
S
S
S
O
O
I/pu
I(/O)
I/O
-
I/O
I
I
S
O
I/O
I/O
I/O
O
I
I
I
[1]
Description
analog output of GREEN or VBS or CVBS signal
analog output of RED or C
test data output for BST
reset input; active LOW
test mode select input for BST
digital supply voltage 2 (3.3 V for I/Os)
digital supply voltage 3 (3.3 V for core)
digital supply voltage 4 (3.3 V for core)
analog supply voltage 3 (3.3 V for oscillator)
vertical synchronization output to monitor
(non-interlaced auxiliary RGB)
horizontal synchronization output to monitor
(non-interlaced auxiliary RGB) or composite sync for
RGB-SCART
test clock input for BST
serial clock input (I
horizontal synchronization output to VGC (optional
input)
to be reserved for future applications
vertical synchronization output to VGC (optional
input)
pixel clock input (looped through)
pixel data 3
digital supply voltage 1 for pins PD11 to PD0,
PIXCLKI, PIXCLKO, FSVGC, VSVGC, HSVGC, CBO
and TVD
interrupt if TV is detected at DAC output
frame synchronization output to Video Graphics
Controller (VGC) (optional input)
serial data input/output (I
composite blanking output to VGC; active LOW
pixel clock output to VGC
pixel data 2
pixel data 1
pixel data 0
SAA7104E; SAA7105E
[6]
[6]
[2]
[2]
[2]
[2]
; MSB
; MSB
; MSB
; MSB
2
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
C-bus) with inactive output path
4 with C
5 with C
6 with C
7 with C
[3]
[3]
2
C-bus)
R
Digital video encoder
or C or CVBS signal
[3]
B
B
B
B
-Y-C
-Y-C
-Y-C
-Y-C
[6]
R
R
R
R
4 : 2 : 2
4 : 2 : 2
4 : 2 : 2
4 : 2 : 2
Section
[6]
7 of 78
7.1.