SAA7105E/V1/G NXP Semiconductors, SAA7105E/V1/G Datasheet - Page 9

• Manufacturer Part Number: SAA7105E/V1/G
• Description: Video ICs PC-DENC
• Manufacturer: NXP Semiconductors

Specifications of SAA7105E/V1/G

• Adc/dac Resolution: 10b
• Screening Level: Commercial
• Package Type: LBGA
• Pin Count: 156
• Lead Free Status / RoHS Status: Compliant
• Other names: SAA7105E/V1/G,557

Philips Semiconductors
SAA7104E_SAA7105E_2
Product data sheet
7.1 Reset conditions
In order to display interlaced RGB signals through a euro-connector TV set, a separate
digital composite sync signal (pin HSM_CSYNC) can be generated; it can be advanced
up to 31 periods of the 27 MHz crystal clock in order to be adapted to the RGB processing
of a TV set.
The SAA7104E; SAA7105E synthesizes all necessary internal signals, color subcarrier
frequency and synchronization signals from that clock.
Wide screen signalling data can be loaded via the I
standards using a 50 Hz field rate.
VPS data for program dependent automatic start and stop of such featured VCRs is
loadable via the I
The IC also contains closed caption and extended data services encoding (line 21), and
supports teletext insertion for the appropriate bit stream format at a 27 MHz clock rate
(see
system into line 20 of every field (525/60 line counting).
A number of possibilities are provided for setting different video parameters such as:
To activate the reset a pulse at least of 2 crystal clocks duration is required.
During reset (RESET = LOW) plus an extra 32 crystal clock periods, FSVGC, VSVGC,
CBO, HSVGC and TTX_SRES are set to input mode and HSM_CSYNC and VSM are set
to 3-state. A reset also forces the I
sets it into receive condition.
After reset, the state of the I/Os and other functions is defined by the strapping pins until
an I
Table 5:
Pin
FSVGC
VSVGC
CBO
HSVGC
TTXRQ_XCLKO2 LOW
•
•
•
2
Black and blanking level control
Color subcarrier frequency
Variable burst amplitude etc.
C-bus access redefines the corresponding registers; see
Figure
Strapping pins
15). It is also possible to load data for the copy generation management
2
C-bus.
Tied
LOW
HIGH
LOW
HIGH
LOW
HIGH
LOW
HIGH
HIGH
Rev. 02 — 23 December 2005
Preset
NTSC M encoding, PIXCLK fits to 640
PAL B/G encoding, PIXCLK fits to 640
4 : 2 : 2 Y-C
4 : 4 : 4 RGB graphics input (format 3)
input demultiplex phase: LSB = LOW
input demultiplex phase: LSB = HIGH
input demultiplex phase: MSB = LOW
input demultiplex phase: MSB = HIGH
slave (FSVGC, VSVGC and HSVGC are inputs, internal color bar
is active)
master (FSVGC, VSVGC and HSVGC are outputs)
2
C-bus interface to abort any running bus transfer and
B
SAA7104E; SAA7105E
-C
R
graphics input (format 0)
2
C-bus and is inserted into line 23 for
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Table
Digital video encoder
480 graphics input
480 graphics input
5.
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