SAA7105E/V1/G NXP Semiconductors, SAA7105E/V1/G Datasheet - Page 22

• Manufacturer Part Number: SAA7105E/V1/G
• Description: Video ICs PC-DENC
• Manufacturer: NXP Semiconductors

Specifications of SAA7105E/V1/G

• Adc/dac Resolution: 10b
• Screening Level: Commercial
• Package Type: LBGA
• Pin Count: 156
• Lead Free Status / RoHS Status: Compliant
• Other names: SAA7105E/V1/G,557

Philips Semiconductors
SAA7104E_SAA7105E_2
Product data sheet
7.20.3 Horizontal scaler
7.20.4 Vertical scaler
should be set according to
Setting a lower value means that the internal pixel clock is higher and the data get
sampled up. The difference may be 1 at 640
with 320 pixels per line as a rule of thumb. This allows horizontal upscaling by a maximum
factor of 2 respectively 4 (this is the parameter RiePclk).
The equations ensure that the last line of the field has the full number of clock cycles.
Many graphic controllers require this. Note that the bit PCLSY needs to be set to ensure
that there is not even a fraction of a clock left at the end of the field.
XOFS can be chosen arbitrarily, the condition being that XOFS + XPIX
Values given by the VESA display timings are preferred.
HLEN = InPpl
XINC needs to be rounded up, it needs to be set to 0 for a scaling factor of 1.
The input vertical offset can be taken from the assumption that the scaler should just have
finished writing the first line when the encoder starts reading it:
In most cases the vertical offsets will be the same for odd and even fields. The results
should be rounded down.
YPIX = InLin
YSKIP defines the anti-flicker function. 0 means maximum flicker reduction but minimum
vertical bandwidth, 4095 gives no flicker reduction and maximum bandwidth. Note that the
maximum value for YINC is 4095. It might be necessary to reduce the value of YSKIP to
fulfil this requirement.
TPclk
PCL
PCLI
XPIX
XINC
YOFS
YINC
=
=
=
=
=
=
=
TXclk
-------------- -
TPclk
PCLE
InPix
------------ -
----------------------------------------------------------------------------------- -
InPpl integer
OutPix
---------------- -
--------------------- -
InLin
FAL 1716 TXclk
-------------------------------------------------- - 2.5
InPix
OutLin
2
InPpl TPclk
–
+
312.5 1728 TXclk
2
RiePclk
RiePclk
log
-------------------------- -
2
20
------------------ -
RiePclk
4096
log
+
RiePclk
Rev. 02 — 23 December 2005
PCLE
1
2
+
InLin
--------------------- -
YSKIP
---------------- -
OutLin
4095
1
(all frequencies); see
Table
(all frequencies)
+
–
2
60. PCLI may be set to a lower or the same value.
4096
312.5
(60 Hz)
SAA7104E; SAA7105E
(50 Hz) and for the pixel clock generator
YOFS
480 pixels resolution and 2 at resolutions
Table 59
=
FAL 1728 TXclk
-------------------------------------------------- - 2.5
InPpl TPclk
and
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Table
Digital video encoder
60. The divider PCLE
HLEN is fulfilled.
–
(50 Hz)
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