W83628AG Nuvoton Technology Corporation of America, W83628AG Datasheet
W83628AG
Specifications of W83628AG
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W83628AG Summary of contents
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... Nuvoton PCI TO ISA BRIDGE W83628AG W83629AG Revision: 1.2 Date: January, 2008 ...
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... W83628AG & W83629AG Datasheet Revision History PAGES DATES 1 N.A. 07/30/2007 2 34, 38 08/02/2007 3 N.A. 11/01/2007 4 1 11/28/2007 5 11 31/1/2008 Please note that all data and specifications are subject to change without notice. All the trademarks of products and companies mentioned in this data sheet belong to their respective owners. ...
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... Table of Contents – 1. GENERAL DESCRIPTION ......................................................................................................... 1 2. FEATURES ................................................................................................................................. 1 3. PACKAGE ................................................................................................................................... 1 4. ORDERING INFORMATION ...................................................................................................... 1 5. BLOCK DIAGRAM OF W83628AG ............................................................................................ 2 6. BLOCK DIAGRAM OF W83629AG ............................................................................................ 3 7. FUNCTION DESCRIPTION........................................................................................................ 4 7.1 PCI Interface ................................................................................................................... 4 7.2 ISA Interface ................................................................................................................... 5 7.3 Serial IRQ Interface ........................................................................................................ 5 7.4 PC/PCI DMA Interface.................................................................................................... 7 7.5 ISA Bus SYSCLK Clock Generation............................................................................... 8 7 ...
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... WISA_FADCB7-ISA BRIDGE FAST DECODERS # 7 BASE ADDRESS REGISTER 32 10.30 WISA_CTRLREG1-ISA BRIDGE CONTROL REGISTER 1 ........................................ 33 10.31 WISA_CTRLREG2-ISA BRIDGE CONTROL REGISTER 2 ........................................ 34 10.32 WISA_CTRLREG3-ISA BRIDGE CONTROL REGISTER 3 ........................................ 34 10.33 WISA_CTRLREG4-ISA BRIDGE CONTROL REGISTER 4 ........................................ 35 W83628AG & W83629AG Publication Release Date: January, 2008 - II - Revision 1.2 ...
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... WISA_TSTREG-ISA BRIDGE TEST REGISTER ........................................................ 36 11. ABSOLUTE MAXIMUM RATINGS ........................................................................................... 37 12. DC CHARACTERISTICS.......................................................................................................... 37 13. AC CHARACTERISTICS .......................................................................................................... 40 14. WAVEFORMS........................................................................................................................... 43 15. TOP MARKING SPECIFICATION ........................................................................................... 58 16. PACKAGE DIMENSIONS 1 FOR W83628AG (128-PIN PQFP).............................................. 59 17. PACKAGE DIMENSIONS 2 FOR W83629AG (48-PIN LQFP) ................................................ 59 W83628AG & W83629AG Publication Release Date: January, 2008 - III - Revision 1.2 ...
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... GENERAL DESCRIPTION The W83628AG is a PCI-to-ISA bus conversion IC. The W83629AG is a condensed centralizer IC for IRQ and DMA control. W83628AG and W83629AG together form a complete set for the PCI-to-ISA bridge. For the new generation Intel chipsets featuring LPC bus but not supporting ISA bus and slots, the W83628AG plus the W83629AG are the best companion solution for the non-ISA chipset ...
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... BLOCK DIAGRAM OF W83628AG AD[31:0] C/BE[3:0]# PAR FRAME# PCI TRDY# Interface IRDY# STOP# DEVSEL# IDSEL SERR# NOGO PCIRST# PCICLK Signal ISOLATE# Isolation Control 3.3V Power SuppIy 5V W83628AG & W83629AG SA[19:0] SD[15:0] BALE AEN IOCHRDY IOCS16# IOCHK# IOR# ISA IOW# Interface LA[23:17] SBHE# ...
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... BLOCK DIAGRAM OF W83629AG PCIRST# PCI Host & PCICLK Bridge Set NOGO Handshaking Logic HS[2:0] ISAREQ# ISAGNT# SERIRQ 3.3V Power 5V Supply W83628AG & W83629AG DREQ[7:5, 3:0] PC/PCI DMA DACK[7:5, 3:0]# Interface TC Parallel To IRQ[15,14,12:9,7:3] Serial IOCHK# IRQ Publication Release Date: January, 2008 - 3 - Revision 1.2 ...
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... PCI Interface The W83628AG provides a PCI slave/master interface. The slave mode means the PCI cycles are initiated by the PCI Host Bridge or South Bridge chipset. Default is PCI bus cycle information from PCI Host Bridge being received in PCI slave mode. When ISA bus’s MASTER# signal is asserted, the W83628A’ ...
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... PCI. Default is driving/issuing relative legacy ISA bus cycle to ISA bus in ISA master mode. Generally if a valid PCI memory or I/O cycle is received by the W83628AG PCI slave interface, it will be passed to the internal ISA interface and the ISA interface will convert it to correspond to the ISA bus cycle. ...
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... Quiet (Active) Mode: Any device may initiate a Start Frame by driving the IRQSER low for one clock, while the IRQSER is Idle. Continuous (Idle) Mode: Only the Host controller can initiate a Start Frame to update IRQ/Data line information. W83628AG & W83629AG IOCHCK# STOP FRAME FRAME ...
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... Table 6-1 below shows the I/O portion of the DMA cycle generates a PCI I/O cycle to one of the four I/O addresses. The W83628AG will recognize the PCI I/O cycle with the DMA I/O address. These cycles must be qualified by an active ISAGNT# signal to the requesting device DMA I/O address bit 2 is used to indicate DMA Terminal Count cycle ...
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... ISA Bus SYSCLK Clock Generation The W83628AG generates the ISA SYSCLK clock using PCI clock signal. A PCICLK divisor ( programmable through PCI configuration register to generate the ISA SYSCLK clock signal. This provides ISA SYSCLK frequencies 8.33MHz and 11MHz of a typical 33MHz PCICLK. ...
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... PIN CONFIGURATION 8.1 PIN CONFIGURATION FOR W83628AG W83628AG & W83629AG Publication Release Date: January, 2008 - 9 - Revision 1.2 ...
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... PIN CONFIGURATION FOR W83629AG W83628AG & W83629AG Publication Release Date: January, 2008 - 10 - Revision 1.2 ...
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... I/O 18tp3 C/BE[3:0]# 51, PCICLK 47 W83628AG & W83629AG FUNCTION PCI Bus Address and Data Signals. The standard PCI address and data lines. The address is driven with FRAME# assertion; the data is driven or received in following clocks. PCI Bus Command and Byte Enables. During the address phase of a transaction, C/BE[3:0]# define the bus command ...
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... System Error. SERR# can be pulsed active by any PCI agent that detects a system error condition. Parity Signal. The W83628AG generates even parity across AD[31:0] and C/BE[3:0]#. PCI Reset. The W83628AG receives PCIRST reset from the PCI Bus. Publication Release Date: January, 2008 - 12 - LEVEL 3 ...
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... Applying a pull-up resistor (4.7Kohm) to this pin disables ISA bridge subtraction decoder. Isolation Control Input. Isolate active low signal by user programming to control all of the output signals of the W83628AG to Isolation and Tri-state. NOGO, This signal indicates which master initiates the current transaction and whether or not the current bus cycle is targeted for the ISA bus ...
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... ISA bus. The SYSCLK is generated by dividing PCICLK Reset Drive. The W83628AG asserts RSTDRV to reset devices that reside on the ISA Bus. The W83628AG asserts this signal while the PCIRST# is asserted. 16-bit I/O Chip Select. This signal is driven by I/O devices on the ISA Bus to indicate that they support 16-bit I/O bus cycles ...
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... ISA bus cycle is a memory write cycle to an address below 1 Mbyte. Bus Address Latch Enable. BALE is an active high signal asserted by the W83628AG to indicate that the address (SA[19:0], LA[23:17]) and SBHE# signal lines are valid. The LA[23:17] address lines are latched on the trailing edge of BALE ...
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... Power Signals SYMBOL PIN VCC 1, 82, 102, 115 3VCC 27, 46, 64 16, 38, 50, 65, 95, GND 111, 128 9.1.5 NC Pins SYMBOL PIN NC 48 W83628AG & W83629AG I/O FUNCTION PWR 5V Supply. PWR 3.3V Supply. PWR Ground. I/O FUNCTION No Connection. Publication Release Date: January, 2008 - 16 - LEVEL 5V 3 ...
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... W83628AG & W83629AG FUNCTION Handshaking Signals. HS[2:0] are connected to the W83628AG for PCI to ISA SET handshaking signals. NO GO. This signal indicates which master initiates the current transaction and whether or not the current bus cycle is targeted for the ISA bus. This signal is a point-to-point connection between PCI HOST Bridge and the W83628AG ...
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... W83628AG & W83629AG FUNCTION DMA Acknowledge. The DACK# signal indicates that either a DMA channel or an ISA bus master is granted to the ISA bus. Terminal Count. The W83628AG asserts TC to DMA slaves as a terminal count indicator. I/O FUNCTION Serial Interrupt Requested Signals. This signal is to transfer IRQ from the parallel IRQ mode to the serial IRQ mode ...
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... Fast Back to Back. This bit always returns a zero. Bit 8 SERR# Enable. =1 Enable. =0 Disable. Bit 7 Wait Cycle Control (Not supported). Hardwired to zero. Bit 6 Parity Error Response (Not supported). Hardwired to zero. Bit 5 VGA Palette Snoop Enable (Not supported). Hardwired to zero. W83628AG & W83629AG Publication Release Date: January, 2008 - 19 - Revision 1.2 ...
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... This bit is set when the ISA bridge signals a target abortion for a PCI transaction. Software sets this bit writing it. Bit 10:9 DEVSEL# Timing. This 2 bits always return a 01b (medium decode). Bit 8 Data Parity Detected (Not supported) Hardwired to zero. W83628AG & W83629AG Publication Release Date: January, 2008 - 20 - Revision 1.2 ...
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... The class code register is a read-only register and used to identify the ISA bridge. Bit 23:16 Base Class Code. 06h = Bus Bridge Bit 15:8 Sub-Class Code. 01h = PCI to ISA Bridge Bit 7:0 Programming Interface. 00h W83628AG & W83629AG Publication Release Date: January, 2008 - 21 - Revision 1.2 ...
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... When bit 6=1, this 3-bit field defines the additional number of SYSCLKs added to standard 3.5 SYSCLK recovery time for 8 bit I/O 000 =0 SYSCLK 001 =1 SYSCLK 010 =2 SYSCLKs 011 =3 SYSCLKs 100 =4 SYSCLKs 101 =5 SYSCLKs 110 =6 SYSCLKs 111 = 7 SYSCLKs W83628AG & W83629AG Publication Release Date: January, 2008 - 22 - Revision 1.2 ...
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... This bit reflects the inverse state of the IOCHK# pin on the ISA bus. Bit 1 Reserved. Bit 0 Byte Lane Error. This bit is set if the ISA bridge detects an illegal byte lane combination for a PCI I/O cycles. W83628AG & W83629AG Publication Release Date: January, 2008 - 23 - Revision 1.2 ...
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... Read/Write Bit [31:24] High Page Base Address of Fast Memory Decoder #0: PCI A[31:24]. W83628AG will relocate the access within Fast Memory Decoder to ISA bus, but the A[31:24] will be ignored since ISA has SA[23:0] only. Bit [23:14] Low Base Address of Fast Memory Decoder #0:PCI A[23:14] Bit [13:12] Reserved ...
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... Read/Write Bit [31:24] High Page Base Address of Fast Memory Decoder #1: PCI A[31:24]. W83628AG will relocate the access within Fast Memory Decoder to ISA bus, but the A[31:24] will be ignored since ISA has SA[23:0] only. Bit [23:14] Low Base Address of Fast Memory Decoder #1:PCI A[23:14] Bit [13:12] Reserved ...
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... Read/Write Bit [31:24] High Page Base Address of Fast Memory Decoder #2: PCI A[31:24]. W83628AG will relocate the access within Fast Memory Decoder to ISA bus, but the A[31:24] will be ignored, since ISA has SA[23:0] only. Bit [23:14] Low Base Address of Fast Memory Decoder #2:PCI A[23:14] Bit [13:12] Reserved ...
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... Bit [17:16] IO Decoder #0. 00=Subtractive speed, 01=Slow speed, 10=Medium speed, 11=Fast speed Bit 15 Enable IO Decoder #7 Address A[15:12] comparison 1=Enable, 0=Disable Bit 14 Enable IO Decoder #6 Address A[15:12] comparison 1=Enable, 0=Disable W83628AG & W83629AG Publication Release Date: January, 2008 - 27 - Revision 1.2 ...
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... Enable/Disable Fast I/O Address Decoder # 5. Bit 4 Enable/Disable Fast I/O Address Decoder # 4. Bit 3 Enable/Disable Fast I/O Address Decoder # 3. Bit 2 Enable/Disable Fast I/O Address Decoder # 2. Bit 1 Enable/Disable Fast I/O Address Decoder # 1. Bit 0 Enable/Disable Fast I/O Address Decoder # 0. W83628AG & W83629AG Publication Release Date: January, 2008 - 28 - Revision 1.2 ...
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... Attribute: Read/Write This register is used to mask address bits (A7~A0) for fast address decoder # 3. If the corresponding bit of this register is set to 1, the corresponding address bit (A7~A0) is ignored by the faster address decoder # 3. W83628AG & W83629AG Publication Release Date: January, 2008 - 29 - Revision 1.2 ...
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... Attribute: Read/Write This register is used to mask address bits (A7~A0) for fast address decoder # 7. If the corresponding bit of this register is set to 1, the corresponding address bit (A7~A0) is ignored by the faster address decoder # 7. W83628AG & W83629AG Publication Release Date: January, 2008 - 30 - Revision 1.2 ...
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... This register contains the base address for fast address decoder # 3. 10.26 WISA_FADCB4-ISA BRIDGE FAST DECODERS # 4 BASE ADDRESS REGISTER Address Offset: 69h_68h Default Value: 00h_00h Attribute: Read/Write This register contains the base address for fast address decoder # 4. W83628AG & W83629AG Publication Release Date: January, 2008 - 31 - Revision 1.2 ...
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... This register contains the base address for fast address decoder # 6. 10.29 WISA_FADCB7-ISA BRIDGE FAST DECODERS # 7 BASE ADDRESS REGISTER Address Offset: 6Fh_6Eh Default Value: 00h_00h Attribute: Read/Write This register contains the base address for fast address decoder # 7. W83628AG & W83629AG Publication Release Date: January, 2008 - 32 - Revision 1.2 ...
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... Enable High-Address BIOS ROM decoder. This bit can be set/reset by ROMCS# power-on setting during PCIRST# assertion. Bit 0 =0 Normal mode. =1 Disable ISA Bridge subtraction decoder. This bit can be set/reset by HS1 power-on setting during PCIRST# assertion. W83628AG & W83629AG Publication Release Date: January, 2008 - 33 - Revision 1.2 ...
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... Reserved. Always write 0 to this bit. Bit 3 1=Enable IOCHK#, 0=Disable IOCHK# Bit 2 0=Enable IRQ15, 1=Disable IRQ15 Bit 1 0=Enable IRQ14, 1=Disable IRQ14 Bit 0 0=Enable IRQ12, 1=Disable IRQ12 W83628AG & W83629AG =1 Disable IRQ11. =1 Disable IRQ10. =1 Disable IRQ9. =1 Disable IRQ7. =1 Disable IRQ6. =1 Disable IRQ5. =1 Disable IRQ4. =1 Disable IRQ3. ...
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... Bit [31:24] High Page Base Address of Fast Memory Decoder #3: PCI A[31:24]. W83628AG will relocate the access within Fast Memory Decoder to ISA bus, but the A[31:24] will be ignored, since ISA has SA[23:0] only. Bit [23:14] Low Base Address of Fast Memory Decoder #3:PCI A[23:14] Bit [13:12] Reserved ...
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... PIIX4 for test, set the bit to 0. Bit 3 Reserved. No data should be written to this register. Bit 2 Reserved. No data should be written to this register. Bit 1 Reserved. No data should be written to this register. Bit 0 Reserved. No data should be written to this register. W83628AG & W83629AG Publication Release Date: January, 2008 - 36 - Revision 1.2 ...
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... TTL level bi-directional pin with source-sink capability 10t Input Low Voltage V Input High Voltage V Output Low Voltage V OL Output High Voltage V OH Input High Leakage I LIH Input Low Leakage I LIL W83628AG & W83629AG RATING -0.5 to 6.0 -0.5 to Vcc+0 +70 -55 to+ 150 MIN. TYP. MAX. UNIT 0 2 μA +10 μ ...
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... V OL Input High Leakage I LIH Input Low Leakage I LIL I/OD – TTL level bi-directional pin. Open-drain output with 18 mA sink capability 18t Input Low Voltage V IL Input High Voltage V IH W83628AG & W83629AG MIN. TYP. MAX. UNIT 0.8 V 2 μA ...
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... TTL level output pin with source-sink capability 10t Output Low Voltage V OL Output High Voltage V OH OUT - TTL level output pin with source-sink capability of 18mA 18t Output Low Voltage V OL Output High Voltage V OH W83628AG & W83629AG MIN. TYP. MAX. UNIT 0 μA +10 V μA -10 V 0.4 V ...
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... BALE Pulse Width t1a LA[23:17] LA[23:17] Valid Setup t2a to BALE Inactive LA[23:17] Valid Hold t2b from BALE Inactive LA[23:17] Valid Setup t2c 1.5T to MEMx# Active LA[23:17] Valid Setuip t2d to IOx# Active W83628AG & W83629AG TYP. MAX. UNIT mV/ns TYP. MAX. UNIT ...
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... IOX# Inactive Pulse t4f 18T Width 18T SD[15:0] SD[15:0] Read Data t5a 2T Valid Setup to MEMR# SD[15:0] Read Data t5b 2T Valid Setup to IOR# W83628AG & W83629AG TYP. MAX. UNIT COMMENTS 11T ns 8-bit memory cycle 9T ns 16-bit memory cycle 30T ns 8-bit I/O cycle ...
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... Valid Setup to MEMW# Active SD[15:0] Write Data t6b 4T Valid setup to IOW# Active SD[15:0] Write Data t6c 2T Valid Hold from MEMW# Inactive SD[15:0] Write Data t6d 2T Valid Hold from IOW# Inactive W83628AG & W83629AG TYP. MAX. UNIT COMMENTS Publication Release Date: January, 2008 - 42 - Revision 1 ...
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... WAVEFORMS Figure 13-1: PCICLK Waveform Figure 13-2: PCI DEVSEL# Timing Speed with Master Abort Termination W83628AG & W83629AG Publication Release Date: January, 2008 - 43 - Revision 1.2 ...
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... W83628AG & W83629AG SYSCLK tSYSCLK_H Figure 13-3: SYSCLK Waveform Figure 13-4: ISA Memory/I/O Read/Write Access Waveform - 44 - tSYSCLK tSYSCLK_L Publication Release Date: January, 2008 Revision 1.2 ...
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... W83628AG & W83629AG PCI Configuration Read Cycle Medium DEVSEL# Speed Figure 13-5: PCI Configuration Read/Write Cycle Figure 13-6: PCI I/O Read from 8-bit ISA Device with SA=3f8h and BE#=0000b - 45 - PCI Configuration Write Cycle Medium DEVSEL# Speed Publication Release Date: January, 2008 ...
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... W83628AG & W83629AG Figure 13-7: PCI I/O Read from 16-bit ISA Device with SA=210h and BE#=0000b - 46 - Publication Release Date: January, 2008 Revision 1.2 ...
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... W83628AG & W83629AG Figure 13-8: PCI I/O Write to 8-bit ISA Device with Write Data = 1234_5678h, SA=3f8h, and BE#=0000b - 47 - Publication Release Date: January, 2008 Revision 1.2 ...
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... W83628AG & W83629AG Figure 13-9: PCI I/O Write to 16-bit ISA Device with Write Data = 1234_5678h 3f8h, and BE#=0000b - 48 - Publication Release Date: January, 2008 Revision 1.2 ...
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... W83628AG & W83629AG Figure 13-10: PCI Memory Read from 8-bit ISA Device with SA=55_5558h and BE#=0000b - 49 - Publication Release Date: January, 2008 Revision 1.2 ...
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... W83628AG & W83629AG Figure 13-11: PCI Memory Read from 16-bit ISA Device with SA=33ch and BE#=0000b - 50 - Publication Release Date: January, 2008 Revision 1.2 ...
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... W83628AG & W83629AG Figure 13-12: PCI Memory Write to 8-bit ISA Device with Write Data=1234_5678h, SA=778h and BE#=0000b - 51 - Publication Release Date: January, 2008 Revision 1.2 ...
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... W83628AG & W83629AG Figure 13-13: PCI Memory Write to 16-bit ISA Device with Write Data = 1234_5678h, SA=1778h, and BE#=0000b - 52 - Publication Release Date: January, 2008 Revision 1.2 ...
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... W83628AG & W83629AG Figure 13-14: ISA Master Memory Read from PCI with Even Address SA and SBHE#= Publication Release Date: January, 2008 Revision 1.2 ...
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... W83628AG & W83629AG Figure 13-15: ISA Master Memory Read from PCI with Even Address SA and SBHE#= Publication Release Date: January, 2008 Revision 1.2 ...
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... W83628AG & W83629AG Figure 13-16: ISA Master Memory Write to PCI with Even Address SA and SBHE#= Publication Release Date: January, 2008 Revision 1.2 ...
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... Figure 13-17: ISA Master Memory Write to PCI with Even Address SA and SBHE#=1b Figure 13-18: DRQn/DACKn# Coding in PC/PCI DMA Function - 56 - W83628AG & W83629AG Publication Release Date: January, 2008 Revision 1.2 ...
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... Drive ISAREQ# Inactive for One Clock to Signal New Request Information Figure 13-20: DRQn/DACKn# Coding in PC/PCI DMA Function with Drive ISAREQ# Inactive for Two Clocks to Signal New Request Information (Previous DRQn had W83628AG & W83629AG been granted the bus) Publication Release Date: January, 2008 - 57 - Revision 1 ...
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... W83628AG 131AE211113302SA 1st line: Chip logo 2nd line: The type number: W83628AG （the “G” means Pb-free package） 3th line: The tracking code 131 A E 211113302SA 131: Packages made in '01, week 31 A: Assembly house ID revision. A means version A; B means version B 21111330: Wafer production series lot number 2SA: Nuvoton internal use ...
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... PACKAGE DIMENSIONS 1 FOR W83628AG (128-PIN PQFP 102 103 128 See Detail Seating Plane 17. PACKAGE DIMENSIONS 2 FOR W83629AG (48-PIN LQFP See Detail F Seating Plane y W83628AG & W83629AG Symbol Min 0.10 c 0.10 D 13.90 E 19. 17.00 H 23. 0. Note: 1.Dimension D & not include interlead flash ...
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... Nuvoton customers using or selling these products for use in such applications their own risk and agree to fully indemnify Nuvoton for any damages resulting from such improper use or sales. W83628AG & W83629AG Important Notice Publication Release Date: January, 2008 - 60 - ...