W83628AG Nuvoton Technology Corporation of America, W83628AG Datasheet - Page 20

• Manufacturer Part Number: W83628AG
• Manufacturer: Nuvoton Technology Corporation of America

Specifications of W83628AG

• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Operating Temperature (max): 70C
• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

ROMCS#
REFRESH#
ZEROWS#
SMEMR#
SMEMW#
BALE
MEMCS16#
SYMBOL
106
117
119
122
123
PIN
73
75
OUT 18t
OUT 18t
OUT 18t
I/OD 18t
I/O 10t
I/O 18t
I/O
IN t
ROMCS#. This pin is weak pulled-down while
PCIRST is asserted. Applying a pull-up resistor
(4.7K ohm) to this pin enables positive decoder
of BIOS address range (depending on Configure
register 70, bit 3,2). When the BIOS access
range is enabled, the pin is BIOS ROMCS#
output.
Refresh. REFRESH# asserted indicates that a
refresh cycle is in progress, or that an ISA master is
requesting the W83628AG to generate a refresh
cycle. Upon PCIRST#, this signal is tri-stated.
Zero Wait States. An ISA slave asserts ZEROWS#
after its address and command signals are decoded
to indicate that the current cycle can be executed
as an ISA zero wait state cycle. ZEROWS# has no
effect during 16-bit I/O cycles.
Standard Memory Read. SMEMR# asserted
indicates the current ISA bus cycle is a memory
read cycle to an address below 1 Mbyte.
Standard Memory Write. SMEMW# asserted
indicates the current ISA bus cycle is a memory
write cycle to an address below 1 Mbyte.
Bus Address Latch Enable. BALE is an active
high signal asserted by the W83628AG to indicate
that the address (SA[19:0], LA[23:17]) and SBHE#
signal lines are valid.
The LA[23:17] address lines are latched on the
trailing edge of BALE. BALE remains asserted
throughout DMA and ISA master cycles. BALE is
driven low upon PCIRST#.
Memory Chip Select 16. MEMCS16# asserted
indicates that the memory slave supports 16-bit
accesses.
- 15 -
W83628AG & W83629AG
FUNCTION
Publication Release Date: January, 2008
Revision 1.2
LEVEL
5V
5V
5V
5V
5V
5V
5V