W83628AG Nuvoton Technology Corporation of America, W83628AG Datasheet - Page 9

• Manufacturer Part Number: W83628AG
• Manufacturer: Nuvoton Technology Corporation of America

Specifications of W83628AG

• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Operating Temperature (max): 70C
• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

7. FUNCTION DESCRIPTION
The W83628AG and W83629AG support the functional sub-block interfaces described below:
The W83628AG provides a PCI slave/master interface. The slave mode means the PCI cycles are
initiated by the PCI Host Bridge or South Bridge chipset. Default is PCI bus cycle information from PCI
Host Bridge being received in PCI slave mode. When ISA bus’s MASTER# signal is asserted, the
W83628A’s PCI interface as slave mode will be switched to PCI master mode to drive/initiate PCI bus
cycles to PCI bus. The W83628AG supports some positive decodes and implements subtractive
decodes for unclaimed PCI accesses.
The PCI slave interface supports the positive decodes as below:
The PCI master interface will issue PCI cycle for ISA bus master cycle.
The W83628AG and the W83629AG together support PC/PCI DMA. The W83629AG uses dedicated
ISAREQ# and ISAGNT# signals to permit ISA devices’ transfer requests associated with specific DMA
channels. Upon receiving a request and getting control of the PCI bus, South Bridge chipset performs
a two-cycle transfer. For example, if data is to be moved from the peripheral to the main memory, the
chipset will first read data from the peripheral and then write it to the main memory.
When in PC/PCI DMA cycle, the W83629AG DACKn# is decoded from ISAGNT#. As long as the
ISAGNT# and MASTER# signals are asserted and are with an ISA command issued by ISA master,
then the W83628AG PCI master interface will issues a PCI cycle for ISA master.
7.1
PCI configuration register spaces which are positively decode with medium DEVSEL#
timing speed on the Type0 PCI configuration cycle.
Eight IO positively decode space which can be programmed to claim PCI I/O cycle with
Fast/Medium/Slow/Subtractive DEVSEL# timing speed.
Four Memory positively decode spaces which can be programmed to claim PCI Memory
cycle with Fast/Medium/Slow/Substractive DEVSEL# timing speed.
PC/PCI DMA (PPDMA) cycle space:The I/O portion of the DMA cycle generates a PCI I/O
cycle to one of the four I/O addresses of 0000h/0004h/00C0h/00C4h
ISA BIOS ROM boot up scheme: upload boot ROM on ISA bus during system boot up.
Enable/disbale optionally the function through the external pull-up resistor on signal
ROMCS# of the W83628AG. When PCIRST# is asserted, the signal ROMCS# will be
detected and latched. After PCIRST# is released, the latched signal High(1)/Low(0)
means to enable(1)/disable(0) the ISA BIOS ROM boot up function, respectively. The
latched bit can also be disabled/enabled through Type0 PCI configuration cycle.
PCI Interface
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W83628AG & W83629AG
Publication Release Date: January, 2008
Revision 1.2