W83628AG Nuvoton Technology Corporation of America, W83628AG Datasheet - Page 10

• Manufacturer Part Number: W83628AG
• Manufacturer: Nuvoton Technology Corporation of America

Specifications of W83628AG

• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Operating Temperature (max): 70C
• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

The W83628AG provides an ISA bus interface for the subtractive decoded memory and I/O cycles on
PCI. Default is driving/issuing relative legacy ISA bus cycle to ISA bus in ISA master mode. Generally
if a valid PCI memory or I/O cycle is received by the W83628AG PCI slave interface, it will be passed
to the internal ISA interface and the ISA interface will convert it to correspond to the ISA bus cycle.
When ISA bus’s MASTER# signal is asserted, the W83628AG ISA interface as master mode will be
switched to ISA slave mode to receive legacy ISA bus cycles from the ISA bus. That means there is
an ISA command issued by ISA master. The related ISA bus cycle will be passed to PCI master
interface to drive/issue corresponding PCI bus cycle.
The W83629AG supports a serialized IRQ slave which conforms to the specification of “Serialized
IRQ Support for PCI system, rev. 6.0, September 1, 1995”. Two modes, continuous and quiet, are
supported.
The serial IRQ interface provides signal filtering and encoding logic for all legacy parallel ISA IRQ
channels (IRQ15-14, 12-9, 7-3 and IOCHK#) to convert them to serial IRQ on the SERIRQ line. The
IRQ/Data serializer is a Wired-OR structure that simply passes the state of one or more device’s
IRQ(s) and/or Data to the host controller. The transfer can be initiated by either a device or the host
controller. A transfer, called an IRQSER Cycle, consists of three frame types: one Start Frame,
several IRQ/Data Frames, and one Stop Frame.
This protocol uses the PCI Clock as its clock source and conforms to the PCI bus electrical
specification.
PCICLK
IRQSER
Drive Source
7.2
7.3
H=Host Control
Start Frame pulse can be 4-8 clocks wide
ISA Interface
Serial IRQ Interface
Start Frame timing with source sampled a low pulse on IRQ1
IRQ1
SL
or
H
START
SL=Slave Control
Host Controller
START FRAME
H
1
R
T
- 5 -
R=Recovery
IRQ0 FRAME
S
None
W83628AG & W83629AG
R
T
Publication Release Date: January, 2008
T=Turn-around
IRQ1 FRAME
S
IRQ1
R
T
S=Sample
IRQ2 FRAME
S
None
Revision 1.2
R
T