W83628AG Nuvoton Technology Corporation of America, W83628AG Datasheet - Page 25

• Manufacturer Part Number: W83628AG
• Manufacturer: Nuvoton Technology Corporation of America

Specifications of W83628AG

• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Operating Temperature (max): 70C
• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Address Offset:
Default Value:
Attribute:
This register shows status information for PCI bus related events.
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10:9
Bit 8
10.4
PCISTS-PCI STATUS REGISTER
Memory Write and Invalidate Enable (Not supported).
Hardwired to zero.
Parity Error Response (Not supported).
Hardwired to zero.
Bus Master Enable
Hardwired to one. The ISA bridge Bus Masters are always supported to generate a
PCI Bus master cycle.
Memory Space Enable
Hardwired to one. The ISA bridge Memory space is always enabled.
I/O Space Enable
Hardwired to one. The ISA bridge I/O space is always enabled.
Detected Parity Error
Hardwired to zero. The ISA bridge does not check bus parity.
Signaled System Error
This bit is set when ISA bridge asserts SERR# on PCI bus.
Received Master Abort Status
This bit is set when the ISA bridge is target aborted as a master on the PCI bus.
Software sets this bit to 0 by writing a 1 to it.
Received Target Abort Status
This bit is set when the ISA bridge target aborts a PCI transaction as a target.
Software sets this bit to 0 by writing a 1 to it.
Signaled Target Abort Status
DEVSEL# Timing. This 2 bits always return a 01b (medium decode).
Data Parity Detected (Not supported)
Hardwired to zero.
This bit is set when the ISA bridge signals a target abortion for a PCI transaction.
07h_06h
02h_00h
Read/Write
Software sets this bit to 0 by writing a 1 to it.
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W83628AG & W83629AG
Publication Release Date: January, 2008
Revision 1.2