MT48H8M16LFB4-75:J TR Micron Technology Inc, MT48H8M16LFB4-75:J TR Datasheet - Page 37

• Manufacturer Part Number: MT48H8M16LFB4-75:J TR
• Manufacturer: Micron Technology Inc
• Type: Mobile SDRAMr

Specifications of MT48H8M16LFB4-75:J TR

• Organization: 8Mx16
• Density: 128Mb
• Address Bus: 14b
• Access Time (max): 8/5.4ns
• Maximum Clock Rate: 133MHz
• Operating Supply Voltage (typ): 1.8V
• Package Type: VFBGA
• Operating Temp Range: 0C to 70C
• Operating Supply Voltage (max): 1.95V
• Operating Supply Voltage (min): 1.7V
• Supply Current: 70mA
• Pin Count: 54
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Compliant

Figure 14:
Burst Length (BL)
PDF: 09005aef832ff1ea/Source: 09005aef832ff1ac
sdr_mobile_sdram_cmd_op_timing_dia_fr10_08__3.fm - Rev. E 4/09 EN
Mn+2 Mn+1
0
0
1
1
Mode Register Definition
0
1
0
1
n+2 n+1
Mn+2
0
Mode Register Definition
Base mode register
Reserved
Extended mode register
Reserved
BA1
M9
0
1
Read and write accesses to the SDRAM are burst oriented and the BL is programmable,
(see Figure 14). The BL determines the maximum number of column locations that can
be accessed for a given READ or WRITE command. Burst lengths of 1, 2, 4, 8, or contin-
uous locations are available for both the sequential and the interleaved burst types, and
a continuous page burst is available for the sequential type. The continuous page burst
is used in conjunction with the BURST TERMINATE command to generate arbitrary BLs.
Reserved states should not be used, as unknown operation or incompatibility with
future versions may result.
When a READ or WRITE command is issued, a block of columns equal to the BL is effec-
tively selected. All accesses for that burst take place within this block, meaning that the
burst wraps within the block when a boundary is reached. The block is uniquely selected
by A[8:1] when BL = 2, A[8:2] when BL = 4, and A[8:3] when BL = 8. The remaining (least
significant) address bit(s) is (are) used to select the starting location within the block.
Continuous page bursts wrap within the page when the boundary is reached.
Mn+1
0
Programmed burst length
Single location access
BA0
M8
0
–
Write Burst Mode
Mn
An
n
Reserved*
M7
0
–
...
...
...
Normal operation
All other states reserved
Operating Mode
10
A10
M10
WB
M6
0
0
0
0
1
1
1
1
M9
A9
9
Op mode
M5
0
0
1
1
0
0
1
1
M8
A8
8
M4
0
1
0
1
0
1
0
1
M7
A7
7
128Mb: 8 Meg x 16, 4 Meg x 32 Mobile SDRAM
CAS Latency
CAS latency
37
A6
M6
6
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
2
3
5
A5
M5
4
A4
M4
Micron Technology, Inc., reserves the right to change products or specifications without notice.
BT
A3
M3
3
M2
Burst length
0
0
0
0
1
1
1
1
A2
M2
2
M1
*Should be programmed to “0”
0
0
1
1
0
0
1
1
to ensure compatibility
with future devices.
A1
M1
1
M3
M0
0
1
0
1
0
1
0
1
0
1
A0
M0
0
Continuous
Reserved
Reserved
Reserved
M3 = 0
Interleaved
Burst Type
Sequential
1
2
4
8
Address bus
Mode
register (Mx)
Burst Length
©2008 Micron Technology, Inc. All rights reserved.
Register Definition
Reserved
Reserved
Reserved
Reserved
M3 = 1
1
2
4
8