FDC37B787-NS Standard Microsystems (SMSC), FDC37B787-NS Datasheet - Page 121

• Manufacturer Part Number: FDC37B787-NS
• Manufacturer: Standard Microsystems (SMSC)

Specifications of FDC37B787-NS

• Pin Count: 128
• Lead Free Status / RoHS Status: Compliant

GENERAL PURPOSE I/O
The FDC37B78x provides a set of flexible
Input/Output control functions to the system
designer through the 21 dedicated independently
programmable General Purpose I/O pins (GPIO).
The GPIO pins can perform simple I/O or can be
individually configured to provide predefined
alternate functions.
configures all GPIO pins as non-inverting inputs.
Description
Each GPIO port requires a 1-bit data register
RUN STATE GPIO DATA REGISTER ACCESS
The GPIO data registers as well as the Watchdog
Timer Control, and the Soft Power Enable and
Status registers can be accessed by the host
PIN NO.
Note 1. Refer to the section on Either Edge Triggered Interrupt Inputs.
Note 2. At power-up, RD0-7, nROMCS and nROMOE function as the XD Bus. To use RD0-7 for
Note 3. These pins cannot be programmed as open drain pins in their original function.
Note 4. The GPIO Data and Configuration Registers are located in Logical Device 8.
Note 5: This pin defaults to its GPIO function. See Configuration Registers.
QFP
77
78
79
80
81
82
39
91
92
83
84
85
86
87
88
89
90
4
6
2
alternate functions, nROMCS must stay high until those pins are finished being programmed.
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
PCI_CLK
DRVDEN1
nROMCS
nROMOE
RD0
RD1
RD2
RD3
RD4
RD5
RD6
RD7
FUNCTION
DEFAULT
2,3
2,3
2,3
2,3
2,3
2,3
2,3
2,3
TABLE 52 - GENERAL PURPOSE I/O PORT ASSIGNMENTS
2
2
5
VBAT Power-On-Reset
nSMI
nRING
WDT
LED
IRRX2
IRTX2
nMTR1
nDS1
IRQ14
GPIO
IRQ11
IRQ12
IRQ1
IRQ3
IRQ4
IRQ5
IRQ6
IRQ7
IRQ8
IRQ10
FUNC. 1
ALT.
-
EETI
P17
-
-
-
-
-
GPIO
IRQ8
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
FUNC. 2
ALT.
1
123
FUNC. 3
-
-
EETI
-
-
-
-
-
-
nSMI
EETI
EETI
nSMI
LED
nRING
WDT
P17
-
-
-
ALT.
and an 8-bit configuration control register. The
data register for each GPIO port is represented as
a bit in one of three 8-bit GPIO DATA Registers,
GP1, GP5, and GP6. All of the GPIO registers are
located in Logical Device Block No. 8 in the
FDC37B78x device configuration space.
GPIO
available
FDC37B78x is in the Run state. The GPIO ports
with their alternate functions and configuration
state register addresses are listed in. Note: three
bits 5-7 of GP5 are not implemented.
when the chip is in the run state if CR03 Bit[7] = 1.
The host uses an Index and Data port to access
these registers. The Index and Data port power-
on default addresses are 0xEA and 0xEB
respectively. In the configuration state the Index
1
1
1
REGISTER
DATA
4
(CRFA)
(CRF6)
(CRF9)
DATA
(HEX)
GP1
GP5
GP6
at
different
Registers
REGISTER
BIT NO.
DATA
0
1
2
3
4
5
6
7
0
2
3
4
0
1
2
3
4
5
6
7
addresses
are
also
REGISTER
CONFIG.
CRCC
(HEX)
CRC8
CRCA
CRCB
CRD0
CRD1
CRD2
CRD3
CRD4
CRD5
CRD6
CRD7
CRE0
CRE1
CRE2
CRE3
CRE4
CRE5
CRE6
CRE7
when
optionally
4
The
the