FDC37B787-NS Standard Microsystems (SMSC), FDC37B787-NS Datasheet - Page 3

• Manufacturer Part Number: FDC37B787-NS
• Manufacturer: Standard Microsystems (SMSC)

Specifications of FDC37B787-NS

• Pin Count: 128
• Lead Free Status / RoHS Status: Compliant

FEATURES ........................................................................................................................................... 1
GENERAL DESCRIPTION ................................................................................................................. 6
DESCRIPTION OF PIN FUNCTIONS............................................................................................... 7
BUFFER TYPE DESCRIPTIONS .................................................................................................... 11
REFERENCE DOCUMENTS ........................................................................................................... 13
FUNCTIONAL DESCRIPTION......................................................................................................... 14
FLOPPY DISK CONTROLLER....................................................................................................... 16
SERIAL PORT (UART) ..................................................................................................................... 70
INFRARED INTERFACE .................................................................................................................. 88
PARALLEL PORT ............................................................................................................................. 88
IBM XT/AT COMPATIBLE, BI-DIRECTIONAL AND EPP MODES........................................ 90
EXTENDED CAPABILITIES PARALLEL PORT.......................................................................... 96
POWER MANAGEMENT................................................................................................................ 110
BIOS BUFFER.................................................................................................................................. 121
GENERAL PURPOSE I/O .............................................................................................................. 123
SUPER I/O REGISTERS ............................................................................................................... 14
HOST PROCESSOR INTERFACE .............................................................................................. 14
PARALLEL PORT FLOPPY DISK CONTROLLER.................................................................. 108
FDC INTERNAL REGISTERS ................................................................................................. 16
COMMAND SET/DESCRIPTIONS.......................................................................................... 41
Force Write Protect .................................................................................................................. 70
REGISTER DESCRIPTION ...................................................................................................... 70
FDC Power Management ...................................................................................................... 110
UART Power Management ................................................................................................... 115
Parallel Port.............................................................................................................................. 115
V
V
Internal PWRGOOD................................................................................................................ 116
CIRCC PLL Power Control ................................................................................................... 116
32.768 kHz Standby Clock Output...................................................................................... 116
BAT
TR
Support .............................................................................................................................. 115
Support ............................................................................................................................ 115
TABLE OF CONTENTS
3