FDC37B787-NS Standard Microsystems (SMSC), FDC37B787-NS Datasheet - Page 158

• Manufacturer Part Number: FDC37B787-NS
• Manufacturer: Standard Microsystems (SMSC)

Specifications of FDC37B787-NS

• Pin Count: 128
• Lead Free Status / RoHS Status: Compliant

General Purpose Event Status Register 1 (GPE_STS1)
Register Location: <PM1_BLK>+8 System I/O Space
Default Value: 00h on Vbat POR
Attribute: Read/Write (Note 0)
Size: 8-bits
Note 1: This bit is set by hardware and can only be cleared by software writing a one to this bit position
and by Vbat POR. Writing a 0 has no effect.
General Purpose Event Enable Register 1 (GPE_EN1)
Register Location: <PM1_BLK>+9 System I/O Space
Default Value: 00h on Vbat POR
Attribute: Read/Write (Note 0)
Size: 8-bits
Note 0: all bits described as "reserved" in writeable registers must be written with the value 0 when the
register is written.
PME Registers
The power management event function has a PME_Status bit and a PME_En bit. These bits are
defined in the PCI Bus Power Management Interface Specification, Revision 1.0, Draft, Copyright ©
1997, PCI Special Interest Group, Mar. 18, 1997.
The default states for the PME_Status and PME_En bits are controlled by V
PME Status Register (PME_STS)
Register Location: <PM1_BLK>+10h System I/O Space
Default Value: 00h on Vbat POR
Attribute: Read/Write (Note 0)
Size: 8-bits
•
0
1-7
0
1-7
BIT
BIT
The PME_Status bit is set when the FDC37B78x would normally assert the PCI nPME signal,
independent of the state of the PME_En bit. Only active transitions on the PME Wake sources can
set the PME_Status bit.
SCI_STS1
Reserved
SCI_EN1
Reserved
NAME
NAME
D7
D6
This bit is set when the device power management events (PME events) occur.
When enabled, the setting of this bit will generate an SCI Interrupt (Note 1).
Writing a “1” to this bit will clear it if there are no pending PME events. See
Figure 5.
Reserved. These bits always return a value of zero.
When this bit is set, then the enabled device power management events (PME
events) will generate an SCI interrupt. When this bit is reset, device power
management events will not generate an SCI interrupt.
Reserved. These bits always return a value of zero.
D5
RESERVED
D4
D3
D2
160
DESCRIPTION
DESCRIPTION
D1
PME_Status
D0
bat
Power-On-Reset.
DEFAULT
0x00