FDC37B787-NS Standard Microsystems (SMSC), FDC37B787-NS Datasheet - Page 147

• Manufacturer Part Number: FDC37B787-NS
• Manufacturer: Standard Microsystems (SMSC)

Specifications of FDC37B787-NS

• Pin Count: 128
• Lead Free Status / RoHS Status: Compliant

Note 1: All soft power management functions run off of VTR. When VTR is present, it supplies power to
Note 2: Flip Flop 1 is battery backed-up so that it returns the last valid state of the machine.
Note 3: A battery backed-up enable bit in the alarm control register can be set to force Flip Flop 1 in the
Note 4: A battery backed-up enable bit in the alarm control register can be set to force Flip Flop 1 to
Button Input
A transition on the Button input, or on any enabled
A low pulse on the Soft Power Off signal, a Vbat POR, a VTR POR with Vbat<1.2V, or Power Button Override Event causes
nPowerOn to float.
ED;PG = Edge Detect, Pulse Generator
ED;L = Edge Detect and Latch
the RTC. When VTR is not present, Vbat supplies power to the RTC and Flip Flop 1.
soft power management circuit to come up ‘on’ if an alarm occurred when VTR was not
present. This is gated into wakeup circuitry. Refer to the AL_REM_EN Bit description in the
RTC Control Register section for more information.
come up ‘off’ after a VTR POR, see VTR_POR_OFF.
SP1
SPx
FIGURE 3 - SOFT POWER MANAGEMENT FUNCTIONAL DIAGRAM
L
nSPOFF1
nSPOFF1
Button
ENx
EN1
ED; L
ED; L
ED; PG
OFF_EN
OFF_DLY
PWRBTNOR_EN
SPx
inputs causes the nPowerOn output to go active low.
Delay2
nSPOFF
149
VTR_POR_EN
Override
AL_REM_EN
Timer
VTR POR
Soft Power
Off
V
Vbat<1.2V
V
Logic
TR
BAT
Alarm
V
nSPOFF1
TR_
POR With
POR
VTR POR
POR_OFF
PWRBTNOR_STS
Logic
Logic
VTR
nSPOFF1
Flop 1
D
CLR
Flip
Q
Delay1
OFF_DLY
nBINT
Type Output
Open Collector
nPowerOn